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radeon/uvd: enable rate control for hevc encoding

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Set cu_qp_delta_enable_flag on when rate control is enabled, and set it
off when rate control is disabled (e.g. constant qp).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-stable@lists.freedesktop.org

V2: fix typo and add bugzilla info

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
This commit is contained in:
Boyuan Zhang 2019-06-17 15:00:53 -04:00 • committed by Leo Liu
parent 9aaf3aaf5d
commit 5115c25bb8
1 changed files with 7 additions and 1 deletions
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8
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
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@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
enc->enc_pic.hevc_spec_misc.
constrained_intra_pred_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
if (enc->enc_pic.rc_session_init.rate_control_method ==
RENC_UVD_RATE_CONTROL_METHOD_NONE)
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
else {
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
radeon_uvd_enc_code_ue(enc, 0x0);
}
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);