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intel/brw/xe2+: Lower 64-bit integer uadd_sat.

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Fixes failures of CTS tests that currently end up emitting 64-bit
integer ADDs with saturation, which isn't supported by the hardware.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
This commit is contained in:
Francisco Jerez 2023-01-04 12:52:07 -08:00 • committed by Marge Bot
parent 15a10786e3
commit 50daf161f4
1 changed files with 2 additions and 1 deletions
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3
src/intel/compiler/brw_compiler.c
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@ -145,7 +145,8 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_lower_bit_count64 |
nir_lower_bcsel64 | nir_lower_conv64 |
nir_lower_extract64 | nir_lower_scan_reduce_bitwise64 |
nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64);
nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64 |
nir_lower_iadd_sat64 | nir_lower_uadd_sat64);
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {