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ac/surf: Add sparse texture info to radeon_surf.

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For GFX9 I didn't reuse the existing mipmap offset/pitch because
last time we did that there was a revert request from Marek.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
This commit is contained in:
Bas Nieuwenhuizen 2020-12-06 19:13:53 +01:00 • committed by Marge Bot
parent cd5458f367
commit 50bafb85ec
2 changed files with 39 additions and 0 deletions
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29
src/amd/common/ac_surface.c
View file

@ -819,6 +819,18 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config *
else
surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
if (AddrSurfInfoIn->flags.prt) {
if (level == 0) {
surf->prt_tile_width = AddrSurfInfoOut->pitchAlign;
surf->prt_tile_height = AddrSurfInfoOut->heightAlign;
}
if (surf_level->nblk_x >= surf->prt_tile_width &&
surf_level->nblk_y >= surf->prt_tile_height) {
/* +1 because the current level is not in the miptail */
surf->first_mip_tail_level = level + 1;
}
}
surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
/* Clear DCC fields at the beginning. */
@ -1652,6 +1664,23 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
if (ret != ADDR_OK)
return ret;
if (in->flags.prt) {
surf->prt_tile_width = out.blockWidth;
surf->prt_tile_height = out.blockHeight;
for (surf->first_mip_tail_level = 0; surf->first_mip_tail_level < in->numMipLevels;
++surf->first_mip_tail_level) {
if(mip_info[surf->first_mip_tail_level].pitch < out.blockWidth ||
mip_info[surf->first_mip_tail_level].height < out.blockHeight)
break;
}
for (unsigned i = 0; i < in->numMipLevels; i++) {
surf->u.gfx9.prt_level_offset[i] = mip_info[i].offset;
surf->u.gfx9.prt_level_pitch[i] = mip_info[i].pitch;
}
}
if (in->flags.stencil) {
surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
surf->u.gfx9.stencil.epitch =

10
src/amd/common/ac_surface.h
View file

@ -189,6 +189,11 @@ struct gfx9_surf_layout {
bool dcc_retile_use_uint16; /* if all values fit into uint16_t */
uint32_t dcc_retile_num_elements;
void *dcc_retile_map;
/* Offset within slice in bytes, only valid for prt images. */
uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS];
/* Pitch of level in blocks, only valid for prt images. */
uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS];
};
struct radeon_surf {
@ -220,6 +225,11 @@ struct radeon_surf {
* changed by the calculator.
*/
/* Not supported yet for depth + stencil. */
uint8_t first_mip_tail_level;
uint16_t prt_tile_width;
uint16_t prt_tile_height;
/* Tile swizzle can be OR'd with low bits of the BASE_256B address.
* The value is the same for all mipmap levels. Supported tile modes:
* - GFX6: Only macro tiling.