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nvc0/ir: fix subops for IMAD

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Offset was wrong, it's at bit 8, not 4. Also, uses subr instead
of sub when src2 has neg. Similar to GK110 now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
This commit is contained in:
Samuel Pitoiset 2016-09-15 18:11:56 +02:00
parent 9b8b69b3c4
commit 50baaf6bc6
1 changed files with 6 additions and 4 deletions
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10
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
View file

@ -735,9 +735,15 @@ CodeEmitterNVC0::emitUADD(const Instruction *i)
void
CodeEmitterNVC0::emitIMAD(const Instruction *i)
{
uint8_t addOp =
(i->src(2).mod.neg() << 1) | (i->src(0).mod.neg() ^ i->src(1).mod.neg());
assert(i->encSize == 8);
emitForm_A(i, HEX64(20000000, 00000003));
assert(addOp != 3);
code[0] |= addOp << 8;
if (isSignedType(i->dType))
code[0] |= 1 << 7;
if (isSignedType(i->sType))
@ -748,10 +754,6 @@ CodeEmitterNVC0::emitIMAD(const Instruction *i)
if (i->flagsDef >= 0) code[1] |= 1 << 16;
if (i->flagsSrc >= 0) code[1] |= 1 << 23;
if (i->src(2).mod.neg()) code[0] |= 0x10;
if (i->src(1).mod.neg() ^
i->src(0).mod.neg()) code[0] |= 0x20;
if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
code[0] |= 1 << 6;
}