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freedreno/registers: More register prep

Browse source 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
This commit is contained in:
Rob Clark 2025-08-27 08:00:46 -07:00 • committed by Marge Bot
parent 67caa784cd
commit 50ab38092f
12 changed files with 75 additions and 61 deletions
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20
src/freedreno/registers/adreno/a6xx.xml
View file

@ -95,7 +95,15 @@ by a particular renderpass/blit.
</reg32>
<reg32 offset="0x0821" name="CP_HW_FAULT"/>
<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
<bitset name="a6xx_cp_protect_status" inline="yes">
<bitfield name="ADDR" low="0" high="17"/>
<bitfield name="READ" pos="20" type="boolean"/>
<bitfield name="CP_HALTED" pos="21" type="boolean"/>
<bitfield name="ACCESS_VIOLATION" pos="22" type="boolean"/>
</bitset>
<reg32 offset="0x0824" name="CP_PROTECT_STATUS" type="a6xx_cp_protect_status"/>
<reg32 offset="0x0825" name="CP_STATUS_1"/>
<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
@ -157,7 +165,7 @@ by a particular renderpass/blit.
<bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
</reg32>
<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8" variants="A6XX-A7XX">
<reg32 offset="0x0" name="REG" type="uint"/>
</array>
<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
@ -657,7 +665,7 @@ by a particular renderpass/blit.
<reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>
<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="init"/>
<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
<reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="init">
<reg32 offset="0x0e19" name="UCHE_CLIENT_PF" variants="A6XX-A7XX" usage="init">
<bitfield high="7" low="0" name="PERFSEL"/>
</reg32>
<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
@ -805,7 +813,7 @@ by a particular renderpass/blit.
<reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="init"/>
<reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="init"/>
<!-- always 0x03200000 ? -->
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="init"/>
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" variants="A6XX-A7XX" usage="init"/>
<!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
<bitset name="a6xx_reg_xy" inline="yes">
@ -1408,7 +1416,7 @@ by a particular renderpass/blit.
<reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/>
<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="init">
<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="init" variants="A6XX-A7XX">
<bitfield name="UNK7" pos="7" type="boolean"/>
<bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
</reg32>
@ -2442,7 +2450,7 @@ by a particular renderpass/blit.
<array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
<!-- always 0x0 -->
<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="init"/>
<reg32 offset="0x9e72" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A6XX-A7XX" usage="init"/>
<reg32 offset="0xa000" name="VFD_CNTL_0" usage="rp_blit">
<bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>

4
src/freedreno/tests/reference/crash.log
View file

@ -618,7 +618,7 @@ registers:
00000000 0x820: 00000000
00000000 CP_HW_FAULT: 0
00000000 CP_INTERRUPT_STATUS: { 0 }
00000000 CP_PROTECT_STATUS: 0
00000000 CP_PROTECT_STATUS: { ADDR = 0 }
00000707 0x826: 00000707
00000001 0x827: 00000001
1000000009000 CP_SQE_INSTR_BASE: 0x1000000009000
@ -1115,7 +1115,7 @@ registers:
00000000 PC_PERFCTR_PC_SEL[0]+0: 00000000
00000000 0x9e70: 00000000
00000000 0x9e71: 00000000
00000000 PC_UNKNOWN_9E72: 0
00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
00000002 0x9e78: 00000002
00000000 0x9e79: 00000000
00000000 0x9e80: 00000000

10
src/freedreno/tests/reference/crash_prefetch.log
View file

@ -833,7 +833,7 @@ registers:
00000001 0x820: 00000001
00000000 CP_HW_FAULT: 0
00000000 CP_INTERRUPT_STATUS: { 0 }
00000000 CP_PROTECT_STATUS: 0
00000000 CP_PROTECT_STATUS: { ADDR = 0 }
0908261e 0x826: 0908261e
00000001 0x827: 00000001
1000000009000 CP_SQE_INSTR_BASE: 0x1000000009000
@ -1330,7 +1330,7 @@ registers:
00000000 PC_PERFCTR_PC_SEL[0]+0: 00000000
00000000 0x9e70: 00000000
00000000 0x9e71: 00000000
00000000 PC_UNKNOWN_9E72: 0
00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
00000002 0x9e78: 00000002
00000000 0x9e79: 00000000
00000000 0x9e80: 00000000
@ -1972,7 +1972,7 @@ got cmdszdw=38
+ 00000000 VPC_DBG_ECO_CNTL: 0
+ 00000000 VPC_UNKNOWN_9602: FALSE
!+ 0000001f PC_MODE_CNTL: 0x1f
+ 00000000 PC_UNKNOWN_9E72: 0
+ 00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
+ 00000000 VFD_RENDER_MODE: { RENDER_MODE = RENDERING_PASS }
!+ 00000001 VFD_MODE_CNTL: { VERTEX }
+ 00000000 SP_UNKNOWN_A9A8: 0
@ -2281,7 +2281,7 @@ got cmdszdw=38
+ 00000000 VPC_DBG_ECO_CNTL: 0
+ 00000000 VPC_UNKNOWN_9602: FALSE
+ 0000001f PC_MODE_CNTL: 0x1f
+ 00000000 PC_UNKNOWN_9E72: 0
+ 00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
+ 00000000 VFD_RENDER_MODE: { RENDER_MODE = RENDERING_PASS }
+ 00000001 VFD_MODE_CNTL: { VERTEX }
+ 00000000 SP_UNKNOWN_A9A8: 0
@ -5039,7 +5039,7 @@ ESTIMATED CRASH LOCATION!
+ 00000000 VPC_DBG_ECO_CNTL: 0
+ 00000000 VPC_UNKNOWN_9602: FALSE
+ 0000001f PC_MODE_CNTL: 0x1f
+ 00000000 PC_UNKNOWN_9E72: 0
+ 00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
+ 00000000 VFD_RENDER_MODE: { RENDER_MODE = RENDERING_PASS }
+ 00000001 VFD_MODE_CNTL: { VERTEX }
+ 00000000 SP_UNKNOWN_A9A8: 0

6
src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -170,8 +170,8 @@ cmdstream[0]: 265 dwords
write VPC_UNKNOWN_9602 (9602)
VPC_UNKNOWN_9602: FALSE
00000000010581b4: 0000: 40960201 00000000
write PC_UNKNOWN_9E72 (9e72)
PC_UNKNOWN_9E72: 0
write PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE (9e72)
PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
00000000010581bc: 0000: 409e7201 00000000
write TPL1_MODE_CNTL (b309)
TPL1_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | TEXCOORDROUNDMODE = COORD_TRUNCATE | NEARESTMIPSNAP = CLAMP_ROUND_TRUNCATE | DESTDATATYPEOVERRIDE }
@ -321,7 +321,7 @@ cmdstream[0]: 265 dwords
+ 00000000 VPC_RAST_STREAM_CNTL: { STREAM = 0 }
+ 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
+ 00000000 PC_STEREO_RENDERING_CNTL: { VIEWS = 0 }
+ 00000000 PC_UNKNOWN_9E72: 0
+ 00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
+ 00000000 VFD_RENDER_MODE: { RENDER_MODE = RENDERING_PASS }
+ 00000000 VFD_STEREO_RENDERING_CNTL: { VIEWS = 0 }
!+ 00000001 VFD_MODE_CNTL: { VERTEX }

6
src/freedreno/tests/reference/fd-clouds.log
View file

@ -164,8 +164,8 @@ cmdstream[0]: 1023 dwords
write PC_DGEN_RAST_CNTL (9981)
PC_DGEN_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES }
0000000001d911a4: 0000: 48998101 00000003
write PC_UNKNOWN_9E72 (9e72)
PC_UNKNOWN_9E72: 0
write PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE (9e72)
PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
0000000001d911ac: 0000: 409e7201 00000000
write VPC_RAST_CNTL (9108)
VPC_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES }
@ -1026,7 +1026,7 @@ cmdstream[0]: 1023 dwords
+ 00000000 PC_HS_CNTL: { STRIDE_IN_VPC = 0 | CLIP_MASK = 0 }
+ 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
+ 00000000 PC_STEREO_RENDERING_CNTL: { VIEWS = 0 }
+ 00000000 PC_UNKNOWN_9E72: 0
+ 00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
!+ 00000101 VFD_CNTL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 }
!+ fcfcfcfc VFD_CNTL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x }
!+ 0000fcfc VFD_CNTL_2: { REGID_HSRELPATCHID = r63.x | REGID_INVOCATIONID = r63.x }

6
src/freedreno/tests/reference/prefetch-test.log
View file

@ -1412,7 +1412,7 @@ registers:
0012d6ac 0x820: 0012d6ac
00000000 CP_HW_FAULT: 0
00000000 CP_INTERRUPT_STATUS: { 0 }
00000000 CP_PROTECT_STATUS: 0
00000000 CP_PROTECT_STATUS: { ADDR = 0 }
5050f1f1 0x826: 5050f1f1
00000001 0x827: 00000001
1000000009000 CP_SQE_INSTR_BASE: 0x1000000009000
@ -1909,7 +1909,7 @@ registers:
00000000 PC_PERFCTR_PC_SEL[0]+0: 00000000
00000000 0x9e70: 00000000
00000000 0x9e71: 00000000
00000000 PC_UNKNOWN_9E72: 0
00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
00000002 0x9e78: 00000002
00000000 0x9e79: 00000000
000d0742 0x9e80: 000d0742
@ -2560,7 +2560,7 @@ got cmdszdw=416
!+ 0000001f PC_MODE_CNTL: 0x1f
+ 00000000 VPC_RAST_STREAM_CNTL: { STREAM = 0 }
+ 00000000 PC_STEREO_RENDERING_CNTL: { VIEWS = 0 }
+ 00000000 PC_UNKNOWN_9E72: 0
+ 00000000 PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE: 0
+ 00000000 VFD_RENDER_MODE: { RENDER_MODE = RENDERING_PASS }
+ 00000000 VFD_STEREO_RENDERING_CNTL: { VIEWS = 0 }
!+ 00000001 VFD_MODE_CNTL: { VERTEX }

2
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -1796,7 +1796,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
}
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
tu_cs_emit_regs(cs, PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE(CHIP));
tu_cs_emit_regs(cs, A6XX_TPL1_MODE_CNTL(.isammode = ISAMMODE_GL,
.texcoordroundmode = dev->instance->use_tex_coord_round_nearest_even_mode
? COORD_ROUND_NEAREST_EVEN

3
src/gallium/drivers/freedreno/a6xx/fd6_context.h
View file

@ -165,6 +165,7 @@ struct fd6_control {
#define control_ptr(fd6_ctx, member) \
(fd6_ctx)->control_mem, offsetof(struct fd6_control, member)
template <chip CHIP>
static inline void
emit_marker6(fd_cs &cs, int scratch_idx)
{
@ -172,7 +173,7 @@ emit_marker6(fd_cs &cs, int scratch_idx)
if (__EMIT_MARKER) {
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_CP_SCRATCH_REG(scratch_idx, p_atomic_inc_return(&marker_cnt)));
.add(CP_SCRATCH_REG(CHIP, scratch_idx, p_atomic_inc_return(&marker_cnt)));
}
}

4
src/gallium/drivers/freedreno/a6xx/fd6_draw.cc
View file

@ -487,7 +487,7 @@ draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
* (scratch6) and DRAW is enough to "triangulate" the
* particular draw that caused lockup.
*/
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
if (is_indirect(DRAW)) {
assert(num_draws == 1); /* only >1 for direct draws */
@ -553,7 +553,7 @@ draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
}
}
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
flush_streamout<CHIP>(ctx, cs, &emit);

13
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -560,7 +560,7 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit)
const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
const struct ir3_shader_variant *fs = emit->fs;
emit_marker6(cs, 5);
emit_marker6<CHIP>(cs, 5);
/* Special case, we need to re-emit bindless FS state w/ the
* fb-read state appended:
@ -878,13 +878,13 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
}
ncrb.add(A6XX_VPC_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.VPC_DBG_ECO_CNTL));
ncrb.add(A6XX_GRAS_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.GRAS_DBG_ECO_CNTL));
ncrb.add(GRAS_DBG_ECO_CNTL(CHIP, .dword = screen->info->a6xx.magic.GRAS_DBG_ECO_CNTL));
if (CHIP == A6XX)
ncrb.add(HLSQ_DBG_ECO_CNTL(CHIP, .dword = screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL));
ncrb.add(A6XX_SP_CHICKEN_BITS(.dword = screen->info->a6xx.magic.SP_CHICKEN_BITS));
ncrb.add(A6XX_UCHE_UNKNOWN_0E12(.dword = screen->info->a6xx.magic.UCHE_UNKNOWN_0E12));
ncrb.add(A6XX_UCHE_CLIENT_PF(.dword = screen->info->a6xx.magic.UCHE_CLIENT_PF));
ncrb.add(UCHE_UNKNOWN_0E12(CHIP, .dword = screen->info->a6xx.magic.UCHE_UNKNOWN_0E12));
ncrb.add(UCHE_CLIENT_PF(CHIP, .dword = screen->info->a6xx.magic.UCHE_CLIENT_PF));
if (CHIP == A6XX) {
ncrb.add(HLSQ_SHARED_CONSTS(CHIP));
@ -908,7 +908,8 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
ncrb.add(RB_BIN_FOVEAT(CHIP));
}
ncrb.add(A6XX_PC_UNKNOWN_9E72());
ncrb.add(PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE(CHIP));
if (CHIP == A7XX)
ncrb.add(RB_UNKNOWN_8E09(CHIP, 0x4));
}
@ -1114,7 +1115,7 @@ fd6_emit_restore(fd_cs &cs, struct fd_batch *batch)
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd6_emit_ib(cs, fd6_context(ctx)->restore);
fd6_emit_ib<CHIP>(cs, fd6_context(ctx)->restore);
fd6_emit_ccu_cntl<CHIP>(cs, screen, false);
uint32_t dwords;

9
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
View file

@ -285,9 +285,9 @@ template <chip CHIP>
static inline void
fd6_emit_blit(struct fd_context *ctx, fd_cs &cs)
{
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
fd6_event_write<CHIP>(ctx, cs, FD_BLIT);
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
}
static inline bool
@ -372,6 +372,7 @@ void fd6_emit_restore(fd_cs &cs, struct fd_batch *batch);
void fd6_emit_init_screen(struct pipe_screen *pscreen);
template <chip CHIP>
static inline void
fd6_emit_ib(fd_cs &cs, struct fd_ringbuffer *target)
{
@ -380,7 +381,7 @@ fd6_emit_ib(fd_cs &cs, struct fd_ringbuffer *target)
unsigned count = fd_ringbuffer_cmd_count(target);
emit_marker6(cs, 6);
emit_marker6<CHIP>(cs, 6);
for (unsigned i = 0; i < count; i++) {
uint32_t dwords;
@ -392,7 +393,7 @@ fd6_emit_ib(fd_cs &cs, struct fd_ringbuffer *target)
assert(dwords > 0);
}
emit_marker6(cs, 6);
emit_marker6<CHIP>(cs, 6);
}
#endif /* FD6_EMIT_H */

53
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -809,6 +809,7 @@ emit_common_fini(fd_cs &cs, struct fd_batch *batch)
*
* If we aren't using binning pass, this just emits a normal IB.
*/
template <chip CHIP>
static void
emit_conditional_ib(fd_cs &cs, struct fd_batch *batch, const struct fd_tile *tile,
struct fd_ringbuffer *target)
@ -818,14 +819,14 @@ emit_conditional_ib(fd_cs &cs, struct fd_batch *batch, const struct fd_tile *til
* to do for this tile)
*/
if (batch->cleared || !use_hw_binning(batch)) {
fd6_emit_ib(cs, target);
fd6_emit_ib<CHIP>(cs, target);
return;
}
if (target->cur == target->start)
return;
emit_marker6(cs, 6);
emit_marker6<CHIP>(cs, 6);
unsigned count = fd_ringbuffer_cmd_count(target);
@ -852,7 +853,7 @@ emit_conditional_ib(fd_cs &cs, struct fd_batch *batch, const struct fd_tile *til
assert(dwords > 0);
}
emit_marker6(cs, 6);
emit_marker6<CHIP>(cs, 6);
}
template <chip CHIP>
@ -944,10 +945,10 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
set_scissor<CHIP>(cs, 0, 0, gmem->width - 1, gmem->height - 1);
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_VISIBILITY));
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1)
.add(0x1);
@ -979,7 +980,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
trace_start_binning_ib(&batch->trace, cs.ring());
foreach_subpass (subpass, batch) {
emit_lrz<CHIP>(cs, batch, subpass);
fd6_emit_ib(cs, subpass->draw);
fd6_emit_ib<CHIP>(cs, subpass->draw);
}
trace_end_binning_ib(&batch->trace, cs.ring());
@ -1116,7 +1117,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
if (batch->prologue) {
trace_start_prologue(&batch->trace, cs.ring());
fd6_emit_ib(cs, batch->prologue);
fd6_emit_ib<CHIP>(cs, batch->prologue);
trace_end_prologue(&batch->trace, cs.ring());
}
@ -1249,11 +1250,11 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
struct fd6_context *fd6_ctx = fd6_context(ctx);
fd_cs cs(batch->gmem);
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_START) |
A6XX_CP_SET_MARKER_0_USES_GMEM);
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
uint32_t x1 = tile->xoff;
uint32_t y1 = tile->yoff;
@ -1694,13 +1695,14 @@ fd6_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
}
/* before IB to rendering cmds: */
template <chip CHIP>
static void
fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
{
if (batch->tile_loads) {
fd_cs cs(batch->gmem);
trace_start_tile_loads(&batch->trace, cs.ring(), batch->restore);
emit_conditional_ib(cs, batch, tile, batch->tile_loads);
emit_conditional_ib<CHIP>(cs, batch, tile, batch->tile_loads);
trace_end_tile_loads(&batch->trace, cs.ring());
}
}
@ -1874,26 +1876,27 @@ fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
foreach_subpass (subpass, batch) {
if (subpass->subpass_clears) {
trace_start_clears(&batch->trace, cs.ring(), subpass->fast_cleared);
emit_conditional_ib(cs, batch, tile, subpass->subpass_clears);
emit_conditional_ib<CHIP>(cs, batch, tile, subpass->subpass_clears);
trace_end_clears(&batch->trace, cs.ring());
}
emit_lrz<CHIP>(cs, batch, subpass);
fd6_emit_ib(cs, subpass->draw);
fd6_emit_ib<CHIP>(cs, subpass->draw);
}
if (batch->tile_epilogue)
fd6_emit_ib(cs, batch->tile_epilogue);
fd6_emit_ib<CHIP>(cs, batch->tile_epilogue);
}
template <chip CHIP>
static void
fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
{
fd_cs cs(batch->gmem);
if (batch->epilogue)
fd6_emit_ib(cs, batch->epilogue);
fd6_emit_ib<CHIP>(cs, batch->epilogue);
if (use_hw_binning(batch)) {
fd_pkt7(cs, CP_SET_MARKER, 1)
@ -1907,14 +1910,14 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
fd_pkt7(cs, CP_SKIP_IB2_ENABLE_LOCAL, 1)
.add(0x0);
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0(.mode = RM6_BIN_RESOLVE, .uses_gmem = true));
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
if (batch->tile_store) {
trace_start_tile_stores(&batch->trace, cs.ring(), batch->resolve);
emit_conditional_ib(cs, batch, tile, batch->tile_store);
emit_conditional_ib<CHIP>(cs, batch, tile, batch->tile_store);
trace_end_tile_stores(&batch->trace, cs.ring());
}
@ -2019,7 +2022,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
if (!batch->nondraw) {
trace_start_prologue(&batch->trace, cs.ring());
}
fd6_emit_ib(cs, batch->prologue);
fd6_emit_ib<CHIP>(cs, batch->prologue);
if (!batch->nondraw) {
trace_end_prologue(&batch->trace, cs.ring());
}
@ -2062,10 +2065,10 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
crb.add(VPC_SO_OVERRIDE(CHIP, false));
}
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER));
emit_marker6(cs, 7);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1)
.add(0x0);
@ -2115,7 +2118,7 @@ fd6_emit_sysmem(struct fd_batch *batch)
emit_lrz<CHIP>(cs, batch, subpass);
fd6_emit_ib(cs, subpass->draw);
fd6_emit_ib<CHIP>(cs, subpass->draw);
}
}
@ -2128,10 +2131,10 @@ fd6_emit_sysmem_fini(struct fd_batch *batch) assert_dt
emit_common_fini<CHIP>(cs, batch);
if (batch->tile_epilogue)
fd6_emit_ib(cs, batch->tile_epilogue);
fd6_emit_ib<CHIP>(cs, batch->tile_epilogue);
if (batch->epilogue)
fd6_emit_ib(cs, batch->epilogue);
fd6_emit_ib<CHIP>(cs, batch->epilogue);
fd_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1)
.add(0x0);
@ -2153,9 +2156,9 @@ fd6_gmem_init(struct pipe_context *pctx)
ctx->emit_tile_init = fd6_emit_tile_init<CHIP>;
ctx->emit_tile_prep = fd6_emit_tile_prep<CHIP>;
ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
ctx->emit_tile_renderprep = fd6_emit_tile_renderprep<CHIP>;
ctx->emit_tile = fd6_emit_tile<CHIP>;
ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem<CHIP>;
ctx->emit_tile_fini = fd6_emit_tile_fini<CHIP>;
ctx->emit_sysmem_prep = fd6_emit_sysmem_prep<CHIP>;
ctx->emit_sysmem = fd6_emit_sysmem<CHIP>;