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broadcom/compiler: add a set_a_flags_for_subgroup helper
We will need this in the future to implement more subgroup operations, so make this code available in a helper. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>
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1 changed files with 29 additions and 24 deletions
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@ -2784,6 +2784,34 @@ emit_load_local_invocation_index(struct v3d_compile *c)
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vir_uniform_ui(c, 32 - c->local_invocation_index_bits));
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}
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/* Various subgroup operations rely on the A flags, so this helper ensures that
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* A flags represents currently active lanes in the subgroup.
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*/
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static void
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set_a_flags_for_subgroup(struct v3d_compile *c)
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{
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/* MSF returns 0 for disabled lanes in compute shaders so
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* PUSHZ will set A=1 for disabled lanes. We want the inverse
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* of this but we don't have any means to negate the A flags
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* directly, but we can do it by repeating the same operation
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* with NORZ (A = ~A & ~Z).
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*/
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assert(c->s->info.stage == MESA_SHADER_COMPUTE);
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vir_set_pf(c, vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
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vir_set_uf(c, vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_UF_NORZ);
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/* If we are under non-uniform control flow we also need to
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* AND the A flags with the current execute mask.
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*/
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if (vir_in_nonuniform_control_flow(c)) {
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const uint32_t bidx = c->cur_block->index;
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vir_set_uf(c, vir_XOR_dest(c, vir_nop_reg(),
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c->execute,
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vir_uniform_ui(c, bidx)),
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V3D_QPU_UF_ANDZ);
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}
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}
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static void
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ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
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{
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@ -3251,30 +3279,7 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
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break;
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case nir_intrinsic_elect: {
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/* Flafirst reads A flags so we need to make sure it reflects
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* currently active lanes.
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*
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* MSF returns 0 for disabled lanes in compute shaders so
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* PUSHZ will set A=1 for disabled lanes. We want the inverse
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* of this but we don't have any means to negate the A flags
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* directly, but we can do it by repeating the same operation
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* with NORZ (A = ~A & ~Z).
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*/
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assert(c->s->info.stage == MESA_SHADER_COMPUTE);
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vir_set_pf(c, vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
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vir_set_uf(c, vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_UF_NORZ);
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/* If we are under non-uniform control flow we also need to
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* AND the A flags with the current execute mask.
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*/
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if (vir_in_nonuniform_control_flow(c)) {
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const uint32_t bidx = c->cur_block->index;
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vir_set_uf(c, vir_XOR_dest(c, vir_nop_reg(),
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c->execute,
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vir_uniform_ui(c, bidx)),
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V3D_QPU_UF_ANDZ);
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}
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set_a_flags_for_subgroup(c);
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struct qreg first = vir_FLAFIRST(c);
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/* Produce a boolean result from Flafirst */
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