From 4ffe1a9f9e6d123408482dcee08d56c8baeee074 Mon Sep 17 00:00:00 2001
From: Jordan Justen <jordan.l.justen@intel.com>
Date: Thu, 13 Apr 2023 15:15:01 -0700
Subject: [PATCH] intel/brw: Fix SSBO/shared load offset register size for Xe2

Rework:
 * Ken: Reword commit message

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29273>
---
 src/intel/compiler/brw_fs_nir.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 3d7463af6d3..44f150aa166 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -6559,7 +6559,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
 
       const nir_src load_offset = is_ssbo ? instr->src[1] : instr->src[0];
       if (nir_src_is_const(load_offset)) {
-         fs_reg addr = ubld8.MOV(brw_imm_ud(nir_src_as_uint(load_offset)));
+         const fs_builder &ubld = devinfo->ver >= 20 ? ubld16 : ubld8;
+         fs_reg addr = ubld.MOV(brw_imm_ud(nir_src_as_uint(load_offset)));
          srcs[SURFACE_LOGICAL_SRC_ADDRESS] = component(addr, 0);
       } else {
          srcs[SURFACE_LOGICAL_SRC_ADDRESS] =