diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h index ba124d48a98..45999136cbf 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h @@ -944,10 +944,8 @@ void vpe10_dpp_dscl_set_scale_ratio(struct dpp *dpp, const struct scaler_data *d void vpe10_dpp_dscl_set_taps(struct dpp *dpp, const struct scaler_data *scl_data); -void vpe10_dpp_dscl_set_scl_filter(struct dpp *dpp, const struct scaler_data *scl_data, - enum vpe10_dscl_mode_sel scl_mode, bool chroma_coef_mode); - -void vpe10_dpp_dscl_set_dscl_mode(struct dpp *dpp, enum vpe10_dscl_mode_sel dscl_mode); +void vpe10_dpp_dscl_set_scl_filter_and_dscl_mode(struct dpp *dpp, + const struct scaler_data *scl_data, enum vpe10_dscl_mode_sel scl_mode, bool chroma_coef_mode); enum vpe10_dscl_mode_sel vpe10_dpp_dscl_get_dscl_mode(const struct scaler_data *data); diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h index 4ab4e9c2284..c94e5d0ab9f 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h @@ -1404,7 +1404,7 @@ void vpe10_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc); void vpe10_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, enum mpc_mux_topsel topsel, enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, - enum mpc_mux_oppid oppid, enum mpcc_blend_mode blend_mode); + enum mpc_mux_oppid oppid); void vpe10_mpc_program_mpcc_blending( struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg); diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h index 372530edd4c..72a4821680e 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_opp.h @@ -180,19 +180,15 @@ void vpe10_opp_set_clamping( void vpe10_opp_set_dyn_expansion(struct opp *opp, bool enable, enum color_depth color_dpth); -void vpe10_opp_set_truncation(struct opp *opp, const struct bit_depth_reduction_params *params); - -void vpe10_opp_set_spatial_dither(struct opp *opp, const struct bit_depth_reduction_params *params); - void vpe10_opp_program_bit_depth_reduction( - struct opp *opp, const struct bit_depth_reduction_params *fmt_bit_depth); + struct opp *opp, const struct bit_depth_reduction_params *params); void vpe10_opp_program_fmt(struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth, - struct clamping_and_pixel_encoding_params *clamping); + struct fmt_control_params *fmt_ctrl, struct clamping_and_pixel_encoding_params *clamping); -void vpe10_opp_program_pipe_alpha(struct opp *opp, uint16_t alpha); +void vpe10_opp_program_fmt_control(struct opp *opp, struct fmt_control_params *fmt_ctrl); -void vpe10_opp_program_pipe_bypass(struct opp *opp, bool enable); +void vpe10_opp_program_pipe_control(struct opp *opp, const struct opp_pipe_control_params *params); void vpe10_opp_program_pipe_crc(struct opp *opp, bool enable); #ifdef __cplusplus diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h index a1fce255f49..268fe953658 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h @@ -78,7 +78,8 @@ void vpe10_calculate_dst_viewport_and_active( struct segment_ctx *segment_ctx, uint32_t max_seg_width); void vpe10_create_stream_ops_config(struct vpe_priv *vpe_priv, uint32_t pipe_idx, - struct stream_ctx *stream_ctx, struct vpe_cmd_input *cmd_input, enum vpe_cmd_ops ops); + struct stream_ctx *stream_ctx, struct vpe_cmd_input *cmd_input, enum vpe_cmd_ops ops, + enum mpcc_blend_mode blend_mode); void vpe10_get_bufs_req(struct vpe_priv *vpe_priv, struct vpe_bufs_req *req); diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c index 52d294f5f89..d57504b9860 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c @@ -484,6 +484,6 @@ bool vpe10_dpp_validate_number_of_taps(struct dpp *dpp, struct scaler_data *scl_ void vpe10_dpp_program_crc(struct dpp *dpp, bool enable) { PROGRAM_ENTRY(); - REG_UPDATE(VPDPP_CRC_CTRL, VPDPP_CRC_EN, enable); + REG_SET(VPDPP_CRC_CTRL, REG_DEFAULT(VPDPP_CRC_CTRL), VPDPP_CRC_EN, enable); } diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c index d755fe8d6cd..9a13d4dda99 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_cm.c @@ -132,21 +132,21 @@ static void vpe10_dpp_program_gammcor_lut( REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), REG_FIELD_MASK(VPCM_GAMCOR_LUT_DATA), CM_PWL_R); } else { - REG_UPDATE(VPCM_GAMCOR_LUT_CONTROL, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 4); + REG_SET(VPCM_GAMCOR_LUT_CONTROL, 0, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 4); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), REG_FIELD_MASK(VPCM_GAMCOR_LUT_DATA), CM_PWL_R); REG_SET(VPCM_GAMCOR_LUT_INDEX, 0, VPCM_GAMCOR_LUT_INDEX, 0); - REG_UPDATE(VPCM_GAMCOR_LUT_CONTROL, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 2); + REG_SET(VPCM_GAMCOR_LUT_CONTROL, 0, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 2); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_green, num, REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), REG_FIELD_MASK(VPCM_GAMCOR_LUT_DATA), CM_PWL_G); REG_SET(VPCM_GAMCOR_LUT_INDEX, 0, VPCM_GAMCOR_LUT_INDEX, 0); - REG_UPDATE(VPCM_GAMCOR_LUT_CONTROL, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 1); + REG_SET(VPCM_GAMCOR_LUT_CONTROL, 0, VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, 1); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_blue, num, REG_OFFSET(VPCM_GAMCOR_LUT_DATA), REG_FIELD_SHIFT(VPCM_GAMCOR_LUT_DATA), diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c index 416129f156e..e0957f0e732 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp_dscl.c @@ -67,14 +67,6 @@ enum vpe10_dscl_mode_sel vpe10_dpp_dscl_get_dscl_mode(const struct scaler_data * return DSCL_MODE_SCALING_420_YCBCR_ENABLE; } -void vpe10_dpp_dscl_set_dscl_mode(struct dpp *dpp, enum vpe10_dscl_mode_sel dscl_mode) -{ - - PROGRAM_ENTRY(); - - REG_SET(VPDSCL_MODE, 0, VPDSCL_MODE, dscl_mode); -} - static void dpp1_dscl_set_recout(struct dpp *dpp, const struct vpe_rect *recout) { @@ -169,8 +161,8 @@ void vpe10_dpp_dscl_set_scaler_filter(struct dpp *dpp, uint32_t taps, } } -void vpe10_dpp_dscl_set_scl_filter(struct dpp *dpp, const struct scaler_data *scl_data, - enum vpe10_dscl_mode_sel scl_mode, bool chroma_coef_mode) +void vpe10_dpp_dscl_set_scl_filter_and_dscl_mode(struct dpp *dpp, + const struct scaler_data *scl_data, enum vpe10_dscl_mode_sel scl_mode, bool chroma_coef_mode) { const uint16_t *filter_h = NULL; @@ -180,41 +172,44 @@ void vpe10_dpp_dscl_set_scl_filter(struct dpp *dpp, const struct scaler_data *sc PROGRAM_ENTRY(); - if (scl_data->polyphase_filter_coeffs == 0) /*no externally provided set of coeffs and taps*/ - { - filter_h = (uint16_t *)dpp1_dscl_get_filter_coeffs_64p( - (int)scl_data->taps.h_taps, scl_data->ratios.horz); - filter_v = - dpp1_dscl_get_filter_coeffs_64p((int)scl_data->taps.v_taps, scl_data->ratios.vert); - } else { - filter_h = (const uint16_t *)&scl_data->polyphase_filter_coeffs->horiz_polyphase_coeffs; - filter_v = (const uint16_t *)&scl_data->polyphase_filter_coeffs->vert_polyphase_coeffs; - } - if (filter_h != NULL) - vpe10_dpp_dscl_set_scaler_filter( - dpp, scl_data->taps.h_taps, SCL_COEF_LUMA_HORZ_FILTER, filter_h); - - if (filter_v != NULL) - vpe10_dpp_dscl_set_scaler_filter( - dpp, scl_data->taps.v_taps, SCL_COEF_LUMA_VERT_FILTER, filter_v); - - if (chroma_coef_mode) { - - filter_h_c = - dpp1_dscl_get_filter_coeffs_64p((int)scl_data->taps.h_taps_c, scl_data->ratios.horz_c); - filter_v_c = - dpp1_dscl_get_filter_coeffs_64p((int)scl_data->taps.v_taps_c, scl_data->ratios.vert_c); - - if (filter_h_c != NULL) + if (scl_mode != DSCL_MODE_DSCL_BYPASS) { + if (scl_data->polyphase_filter_coeffs == + 0) /*no externally provided set of coeffs and taps*/ + { + filter_h = (uint16_t *)dpp1_dscl_get_filter_coeffs_64p( + (int)scl_data->taps.h_taps, scl_data->ratios.horz); + filter_v = + dpp1_dscl_get_filter_coeffs_64p((int)scl_data->taps.v_taps, scl_data->ratios.vert); + } else { + filter_h = (const uint16_t *)&scl_data->polyphase_filter_coeffs->horiz_polyphase_coeffs; + filter_v = (const uint16_t *)&scl_data->polyphase_filter_coeffs->vert_polyphase_coeffs; + } + if (filter_h != NULL) vpe10_dpp_dscl_set_scaler_filter( - dpp, scl_data->taps.h_taps_c, SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c); + dpp, scl_data->taps.h_taps, SCL_COEF_LUMA_HORZ_FILTER, filter_h); - if (filter_v_c != NULL) + if (filter_v != NULL) vpe10_dpp_dscl_set_scaler_filter( - dpp, scl_data->taps.v_taps_c, SCL_COEF_CHROMA_VERT_FILTER, filter_v_c); + dpp, scl_data->taps.v_taps, SCL_COEF_LUMA_VERT_FILTER, filter_v); + + if (chroma_coef_mode) { + + filter_h_c = dpp1_dscl_get_filter_coeffs_64p( + (int)scl_data->taps.h_taps_c, scl_data->ratios.horz_c); + filter_v_c = dpp1_dscl_get_filter_coeffs_64p( + (int)scl_data->taps.v_taps_c, scl_data->ratios.vert_c); + + if (filter_h_c != NULL) + vpe10_dpp_dscl_set_scaler_filter( + dpp, scl_data->taps.h_taps_c, SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c); + + if (filter_v_c != NULL) + vpe10_dpp_dscl_set_scaler_filter( + dpp, scl_data->taps.v_taps_c, SCL_COEF_CHROMA_VERT_FILTER, filter_v_c); + } } - REG_UPDATE(VPDSCL_MODE, SCL_CHROMA_COEF_MODE, chroma_coef_mode); + REG_SET_2(VPDSCL_MODE, 0, VPDSCL_MODE, scl_mode, SCL_CHROMA_COEF_MODE, chroma_coef_mode); } void vpe10_dpp_dscl_set_lb(struct dpp *dpp, const struct line_buffer_params *lb_params, @@ -332,9 +327,8 @@ void vpe10_dpp_set_frame_scaler(struct dpp *dpp, const struct scaler_data *scl_d if (dscl_mode != DSCL_MODE_DSCL_BYPASS) vpe10_dpp_power_on_dscl(dpp, true); - vpe10_dpp_dscl_set_dscl_mode(dpp, dscl_mode); - if (dscl_mode == DSCL_MODE_DSCL_BYPASS) { + vpe10_dpp_dscl_set_scl_filter_and_dscl_mode(dpp, scl_data, dscl_mode, ycbcr); vpe10_dpp_power_on_dscl(dpp, false); return; } @@ -342,5 +336,5 @@ void vpe10_dpp_set_frame_scaler(struct dpp *dpp, const struct scaler_data *scl_d vpe10_dpp_dscl_set_lb(dpp, &scl_data->lb_params, LB_MEMORY_CONFIG_0); vpe10_dpp_dscl_set_scale_ratio(dpp, scl_data); vpe10_dpp_dscl_set_taps(dpp, scl_data); - vpe10_dpp_dscl_set_scl_filter(dpp, scl_data, dscl_mode, ycbcr); + vpe10_dpp_dscl_set_scl_filter_and_dscl_mode(dpp, scl_data, dscl_mode, ycbcr); } diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c index 4d5196e6af6..c9477db0982 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c @@ -67,7 +67,7 @@ void vpe10_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc) void vpe10_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, enum mpc_mux_topsel topsel, enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, - enum mpc_mux_oppid oppid, enum mpcc_blend_mode blend_mode) + enum mpc_mux_oppid oppid) { PROGRAM_ENTRY(); @@ -77,7 +77,6 @@ void vpe10_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, REG_SET(VPMPCC_BOT_SEL, 0, VPMPCC_BOT_SEL, botsel); REG_SET(VPMPC_OUT_MUX, 0, VPMPC_OUT_MUX, outmux); REG_SET(VPMPCC_VPOPP_ID, 0, VPMPCC_VPOPP_ID, oppid); - REG_UPDATE(VPMPCC_CONTROL, VPMPCC_MODE, blend_mode); } void vpe10_mpc_program_mpcc_blending( @@ -90,11 +89,12 @@ void vpe10_mpc_program_mpcc_blending( VPE_ASSERT(mpcc_idx == MPC_MPCCID_0); - REG_UPDATE_7(VPMPCC_CONTROL, VPMPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, - VPMPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, - VPMPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, VPMPCC_GLOBAL_ALPHA, - blnd_cfg->global_alpha, VPMPCC_GLOBAL_GAIN, blnd_cfg->global_gain, VPMPCC_BG_BPC, - blnd_cfg->background_color_bpc, VPMPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode); + REG_SET_8(VPMPCC_CONTROL, REG_DEFAULT(VPMPCC_CONTROL), VPMPCC_MODE, blnd_cfg->blend_mode, + VPMPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, VPMPCC_ALPHA_MULTIPLIED_MODE, + blnd_cfg->pre_multiplied_alpha, VPMPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, + VPMPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, VPMPCC_GLOBAL_GAIN, blnd_cfg->global_gain, + VPMPCC_BG_BPC, blnd_cfg->background_color_bpc, VPMPCC_BOT_GAIN_MODE, + blnd_cfg->bottom_gain_mode); REG_SET(VPMPCC_TOP_GAIN, 0, VPMPCC_TOP_GAIN, blnd_cfg->top_gain); REG_SET(VPMPCC_BOT_GAIN_INSIDE, 0, VPMPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); @@ -178,13 +178,16 @@ void vpe10_mpc_power_on_ogam_lut(struct mpc *mpc, bool power_on) * * Memory low power mode is controlled during MPC OGAM LUT init. */ - REG_UPDATE(VPMPCC_MEM_PWR_CTRL, VPMPCC_OGAM_MEM_PWR_DIS, power_on ? 1 : 0); + REG_SET(VPMPCC_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MEM_PWR_CTRL), VPMPCC_OGAM_MEM_PWR_DIS, + power_on ? 1 : 0); /* Wait for memory to be powered on - we will not be able to write to it otherwise. */ if (power_on) { // dummy write as delay in power up - REG_UPDATE(VPMPCC_MEM_PWR_CTRL, VPMPCC_OGAM_MEM_PWR_DIS, power_on ? 1 : 0); - REG_UPDATE(VPMPCC_MEM_PWR_CTRL, VPMPCC_OGAM_MEM_PWR_DIS, power_on ? 1 : 0); + REG_SET(VPMPCC_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MEM_PWR_CTRL), VPMPCC_OGAM_MEM_PWR_DIS, + power_on ? 1 : 0); + REG_SET(VPMPCC_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MEM_PWR_CTRL), VPMPCC_OGAM_MEM_PWR_DIS, + power_on ? 1 : 0); } } @@ -359,7 +362,7 @@ static void vpe10_mpc_program_luta(struct mpc *mpc, const struct pwl_params *par } static void vpe10_mpc_program_ogam_pwl( - struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num) + struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num, uint8_t ogam_lut_host_sel) { PROGRAM_ENTRY(); @@ -372,21 +375,27 @@ static void vpe10_mpc_program_ogam_pwl( REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), REG_FIELD_MASK(VPMPCC_OGAM_LUT_DATA), CM_PWL_R); } else { - REG_UPDATE(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 4); + REG_SET_2(VPMPCC_OGAM_LUT_CONTROL, + 0, // disable READ_DBG, set CONFIG_MODE to diff start/end mode implicitly + VPMPCC_OGAM_LUT_HOST_SEL, ogam_lut_host_sel, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 4); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), REG_FIELD_MASK(VPMPCC_OGAM_LUT_DATA), CM_PWL_R); REG_SET(VPMPCC_OGAM_LUT_INDEX, 0, VPMPCC_OGAM_LUT_INDEX, 0); - REG_UPDATE(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 2); + REG_SET_2(VPMPCC_OGAM_LUT_CONTROL, + 0, // disable READ_DBG, set CONFIG_MODE to diff start/end mode implicitly + VPMPCC_OGAM_LUT_HOST_SEL, ogam_lut_host_sel, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 2); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_green, num, REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), REG_FIELD_MASK(VPMPCC_OGAM_LUT_DATA), CM_PWL_G); REG_SET(VPMPCC_OGAM_LUT_INDEX, 0, VPMPCC_OGAM_LUT_INDEX, 0); - REG_UPDATE(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 1); + REG_SET_2(VPMPCC_OGAM_LUT_CONTROL, + 0, // disable READ_DBG, set CONFIG_MODE to diff start/end mode implicitly + VPMPCC_OGAM_LUT_HOST_SEL, ogam_lut_host_sel, VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 1); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_blue, num, REG_OFFSET(VPMPCC_OGAM_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_OGAM_LUT_DATA), @@ -397,6 +406,7 @@ static void vpe10_mpc_program_ogam_pwl( void vpe10_mpc_set_output_gamma(struct mpc *mpc, const struct pwl_params *params) { PROGRAM_ENTRY(); + uint8_t ogam_lut_host_sel; if (vpe_priv->init.debug.cm_in_bypass || // debug option: put CM in bypass mode vpe_priv->init.debug.bypass_ogam || params == NULL) { // disable OGAM @@ -411,16 +421,17 @@ void vpe10_mpc_set_output_gamma(struct mpc *mpc, const struct pwl_params *params mpc->funcs->power_on_ogam_lut(mpc, true); // configure_ogam_lut as LUT_A and all RGB channels to be written + ogam_lut_host_sel = RAM_LUT_A; REG_SET_2(VPMPCC_OGAM_LUT_CONTROL, 0, // disable READ_DBG, set CONFIG_MODE to diff start/end mode implicitly - VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 7, VPMPCC_OGAM_LUT_HOST_SEL, RAM_LUT_A); + VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, 7, VPMPCC_OGAM_LUT_HOST_SEL, ogam_lut_host_sel); REG_SET(VPMPCC_OGAM_LUT_INDEX, 0, VPMPCC_OGAM_LUT_INDEX, 0); // Always program LUTA in VPE10 vpe10_mpc_program_luta(mpc, params); - vpe10_mpc_program_ogam_pwl(mpc, params->rgb_resulted, params->hw_points_num); + vpe10_mpc_program_ogam_pwl(mpc, params->rgb_resulted, params->hw_points_num, ogam_lut_host_sel); // Assume we prefer to enable_mem_low_power if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) @@ -624,23 +635,16 @@ bool vpe10_mpc_program_shaper(struct mpc *mpc, const struct pwl_params *params) return true; } -static void vpe10_mpc_select_3dlut_ram( - struct mpc *mpc, enum vpe_lut_mode mode, bool is_color_channel_12bits) +static void vpe10_mpc_select_3dlut_ram_and_mask(struct mpc *mpc, enum vpe_lut_mode mode, + bool is_color_channel_12bits, uint32_t ram_selection_mask) { PROGRAM_ENTRY(); VPE_ASSERT(mode == LUT_RAM_A); - REG_UPDATE_2(VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, VPMPCC_MCM_3DLUT_RAM_SEL, - mode == LUT_RAM_A ? 0 : 1, VPMPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits ? 0 : 1); -} - -static void vpe10_mpc_select_3dlut_ram_mask(struct mpc *mpc, uint32_t ram_selection_mask) -{ - PROGRAM_ENTRY(); - - REG_UPDATE( - VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, VPMPCC_MCM_3DLUT_WRITE_EN_MASK, ram_selection_mask); + REG_SET_3(VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, REG_DEFAULT(VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL), + VPMPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, VPMPCC_MCM_3DLUT_30BIT_EN, + is_color_channel_12bits ? 0 : 1, VPMPCC_MCM_3DLUT_WRITE_EN_MASK, ram_selection_mask); REG_SET(VPMPCC_MCM_3DLUT_INDEX, 0, VPMPCC_MCM_3DLUT_INDEX, 0); } @@ -859,30 +863,29 @@ void vpe10_mpc_program_3dlut(struct mpc *mpc, const struct tetrahedral_params *p lut_size = sizeof(params->tetrahedral_9.lut1) / sizeof(params->tetrahedral_9.lut1[0]); } - vpe10_mpc_select_3dlut_ram(mpc, mode, is_12bits_color_channel); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x1); // set mask to LUT0 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x1); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12(mpc, lut0, lut_size0); else vpe10_mpc_set3dlut_ram10(mpc, lut0, lut_size0); // set mask to LUT1 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x2); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x2); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12(mpc, lut1, lut_size); else vpe10_mpc_set3dlut_ram10(mpc, lut1, lut_size); // set mask to LUT2 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x4); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x4); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12(mpc, lut2, lut_size); else vpe10_mpc_set3dlut_ram10(mpc, lut2, lut_size); // set mask to LUT3 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x8); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x8); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12(mpc, lut3, lut_size); else @@ -947,31 +950,29 @@ bool vpe10_mpc_program_3dlut_indirect(struct mpc *mpc, lut_size = tetra9_lut_size; } - vpe10_mpc_select_3dlut_ram(mpc, mode, is_12bits_color_channel); - // set mask to LUT0 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x1); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x1); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12_indirect(mpc, lut0_gpuva, lut_size0); else vpe10_mpc_set3dlut_ram10_indirect(mpc, lut0_gpuva, lut_size0); // set mask to LUT1 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x2); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x2); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12_indirect(mpc, lut1_gpuva, lut_size); else vpe10_mpc_set3dlut_ram10_indirect(mpc, lut1_gpuva, lut_size); // set mask to LUT2 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x4); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x4); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12_indirect(mpc, lut2_gpuva, lut_size); else vpe10_mpc_set3dlut_ram10_indirect(mpc, lut2_gpuva, lut_size); // set mask to LUT3 - vpe10_mpc_select_3dlut_ram_mask(mpc, 0x8); + vpe10_mpc_select_3dlut_ram_and_mask(mpc, mode, is_12bits_color_channel, 0x8); if (is_12bits_color_channel) vpe10_mpc_set3dlut_ram12_indirect(mpc, lut3_gpuva, lut_size); else @@ -1076,14 +1077,15 @@ static void vpe10_mpc_program_1dlut_luta_settings(struct mpc *mpc, const struct vpe10_cm_helper_program_gamcor_xfer_func(config_writer, params, &gam_regs); } -static void vpe10_mpc_program_1dlut_pwl( - struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num, enum cm_type gamma_type) +static void vpe10_mpc_program_1dlut_pwl(struct mpc *mpc, const struct pwl_result_data *rgb, + uint32_t num, enum cm_type gamma_type, bool is_ram_a) { PROGRAM_ENTRY(); uint32_t last_base_value_red; uint32_t last_base_value_green; uint32_t last_base_value_blue; + uint8_t host_sel = (is_ram_a == true) ? 0 : 1; if (gamma_type == CM_DEGAM) { last_base_value_red = rgb[num].red_reg; @@ -1101,21 +1103,24 @@ static void vpe10_mpc_program_1dlut_pwl( REG_FIELD_MASK(VPMPCC_MCM_1DLUT_LUT_DATA), CM_PWL_R); } else { REG_SET(VPMPCC_MCM_1DLUT_LUT_INDEX, 0, VPMPCC_MCM_1DLUT_LUT_INDEX, 0); - REG_UPDATE(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4); + REG_SET_2(VPMPCC_MCM_1DLUT_LUT_CONTROL, 0, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4, + VPMPCC_MCM_1DLUT_LUT_HOST_SEL, host_sel); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_red, num, REG_OFFSET(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_MASK(VPMPCC_MCM_1DLUT_LUT_DATA), CM_PWL_R); REG_SET(VPMPCC_MCM_1DLUT_LUT_INDEX, 0, VPMPCC_MCM_1DLUT_LUT_INDEX, 0); - REG_UPDATE(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2); + REG_SET_2(VPMPCC_MCM_1DLUT_LUT_CONTROL, 0, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2, + VPMPCC_MCM_1DLUT_LUT_HOST_SEL, host_sel); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_green, num, REG_OFFSET(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_MASK(VPMPCC_MCM_1DLUT_LUT_DATA), CM_PWL_G); REG_SET(VPMPCC_MCM_1DLUT_LUT_INDEX, 0, VPMPCC_MCM_1DLUT_LUT_INDEX, 0); - REG_UPDATE(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1); + REG_SET_2(VPMPCC_MCM_1DLUT_LUT_CONTROL, 0, VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1, + VPMPCC_MCM_1DLUT_LUT_HOST_SEL, host_sel); vpe10_cm_helper_program_pwl(config_writer, rgb, last_base_value_blue, num, REG_OFFSET(VPMPCC_MCM_1DLUT_LUT_DATA), REG_FIELD_SHIFT(VPMPCC_MCM_1DLUT_LUT_DATA), @@ -1143,7 +1148,7 @@ void vpe10_mpc_program_1dlut(struct mpc *mpc, const struct pwl_params *params, e vpe10_mpc_configure_1dlut(mpc, true); vpe10_mpc_program_1dlut_luta_settings(mpc, params); - vpe10_mpc_program_1dlut_pwl(mpc, params->rgb_resulted, params->hw_points_num, gamma_type); + vpe10_mpc_program_1dlut_pwl(mpc, params->rgb_resulted, params->hw_points_num, gamma_type, true); REG_SET( VPMPCC_MCM_1DLUT_CONTROL, REG_DEFAULT(VPMPCC_MCM_1DLUT_CONTROL), VPMPCC_MCM_1DLUT_MODE, 2); @@ -1335,6 +1340,6 @@ bool vpe10_mpc_program_movable_cm(struct mpc *mpc, struct transfer_func *func_sh void vpe10_mpc_program_crc(struct mpc *mpc, bool enable) { PROGRAM_ENTRY(); - REG_UPDATE(VPMPC_CRC_CTRL, VPMPC_CRC_EN, enable); + REG_SET(VPMPC_CRC_CTRL, REG_DEFAULT(VPMPC_CRC_CTRL), VPMPC_CRC_EN, enable); } diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c b/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c index a72d28f1d88..5e8fd7c6044 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_opp.c @@ -33,15 +33,13 @@ #define CTX vpe10_opp static struct opp_funcs opp_funcs = { - .program_pipe_alpha = vpe10_opp_program_pipe_alpha, - .program_pipe_bypass = vpe10_opp_program_pipe_bypass, + .program_pipe_control = vpe10_opp_program_pipe_control, .program_pipe_crc = vpe10_opp_program_pipe_crc, .set_clamping = vpe10_opp_set_clamping, - .set_truncation = vpe10_opp_set_truncation, - .set_spatial_dither = vpe10_opp_set_spatial_dither, .program_bit_depth_reduction = vpe10_opp_program_bit_depth_reduction, .set_dyn_expansion = vpe10_opp_set_dyn_expansion, .program_fmt = vpe10_opp_program_fmt, + .program_fmt_control = vpe10_opp_program_fmt_control, }; void vpe10_construct_opp(struct vpe_priv *vpe_priv, struct opp *opp) @@ -98,40 +96,21 @@ void vpe10_opp_set_dyn_expansion(struct opp *opp, bool enable, enum color_depth } } -void vpe10_opp_set_truncation(struct opp *opp, const struct bit_depth_reduction_params *params) +void vpe10_opp_program_bit_depth_reduction( + struct opp *opp, const struct bit_depth_reduction_params *params) { PROGRAM_ENTRY(); - REG_UPDATE_3(VPFMT_BIT_DEPTH_CONTROL, VPFMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED, - VPFMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, VPFMT_TRUNCATE_MODE, - params->flags.TRUNCATE_MODE); -} + if (params->flags.SPATIAL_DITHER_ENABLED == 0) { + /*Disable spatial (random) dithering*/ + REG_SET_9(VPFMT_BIT_DEPTH_CONTROL, REG_DEFAULT(VPFMT_BIT_DEPTH_CONTROL), VPFMT_TRUNCATE_EN, + params->flags.TRUNCATE_ENABLED, VPFMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, + VPFMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE, VPFMT_SPATIAL_DITHER_EN, 0, + VPFMT_SPATIAL_DITHER_MODE, 0, VPFMT_SPATIAL_DITHER_DEPTH, 0, + VPFMT_HIGHPASS_RANDOM_ENABLE, 0, VPFMT_FRAME_RANDOM_ENABLE, 0, VPFMT_RGB_RANDOM_ENABLE, + 0); -void vpe10_opp_set_spatial_dither(struct opp *opp, const struct bit_depth_reduction_params *params) -{ - PROGRAM_ENTRY(); - - /*Disable spatial (random) dithering*/ - REG_UPDATE_6(VPFMT_BIT_DEPTH_CONTROL, VPFMT_SPATIAL_DITHER_EN, 0, VPFMT_SPATIAL_DITHER_MODE, 0, - VPFMT_SPATIAL_DITHER_DEPTH, 0, VPFMT_HIGHPASS_RANDOM_ENABLE, 0, VPFMT_FRAME_RANDOM_ENABLE, - 0, VPFMT_RGB_RANDOM_ENABLE, 0); - - if (params->flags.SPATIAL_DITHER_ENABLED == 0) return; - - /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ - if (params->flags.FRAME_RANDOM == 1) { - if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) { - REG_UPDATE_2(VPFMT_CONTROL, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15, - VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2); - } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { - REG_UPDATE_2(VPFMT_CONTROL, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3, - VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1); - } else - return; - } else { - REG_UPDATE_2(VPFMT_CONTROL, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0, - VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0); } /* Set seed for random values for @@ -159,7 +138,9 @@ void vpe10_opp_set_spatial_dither(struct opp *opp, const struct bit_depth_reduct * 0x80000 YCbCr. */ - REG_UPDATE_6(VPFMT_BIT_DEPTH_CONTROL, + REG_SET_9(VPFMT_BIT_DEPTH_CONTROL, REG_DEFAULT(VPFMT_BIT_DEPTH_CONTROL), VPFMT_TRUNCATE_EN, + params->flags.TRUNCATE_ENABLED, VPFMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, + VPFMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE, /*Enable spatial dithering*/ VPFMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED, /* Set spatial dithering mode @@ -176,35 +157,52 @@ void vpe10_opp_set_spatial_dither(struct opp *opp, const struct bit_depth_reduct VPFMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); } -void vpe10_opp_program_bit_depth_reduction( - struct opp *opp, const struct bit_depth_reduction_params *fmt_bit_depth) +void vpe10_opp_program_fmt_control(struct opp *opp, struct fmt_control_params *fmt_ctrl) { - opp->funcs->set_truncation(opp, fmt_bit_depth); - opp->funcs->set_spatial_dither(opp, fmt_bit_depth); + PROGRAM_ENTRY(); + + REG_SET_2(VPFMT_CONTROL, REG_DEFAULT(VPFMT_CONTROL), VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, + fmt_ctrl->fmt_spatial_dither_frame_counter_max, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, + fmt_ctrl->fmt_spatial_dither_frame_counter_bit_swap); } void vpe10_opp_program_fmt(struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth, - struct clamping_and_pixel_encoding_params *clamping) + struct fmt_control_params *fmt_ctrl, struct clamping_and_pixel_encoding_params *clamping) { opp->funcs->program_bit_depth_reduction(opp, fmt_bit_depth); + + /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ + if (fmt_bit_depth->flags.FRAME_RANDOM == 1) { + if (fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH == 0 || + fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH == 1) { + fmt_ctrl->fmt_spatial_dither_frame_counter_max = 15; + fmt_ctrl->fmt_spatial_dither_frame_counter_bit_swap = 2; + } else if (fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH == 2) { + fmt_ctrl->fmt_spatial_dither_frame_counter_max = 3; + fmt_ctrl->fmt_spatial_dither_frame_counter_bit_swap = 1; + } else { + fmt_ctrl->fmt_spatial_dither_frame_counter_max = 0; + fmt_ctrl->fmt_spatial_dither_frame_counter_bit_swap = 0; + } + } else { + fmt_ctrl->fmt_spatial_dither_frame_counter_max = 0; + fmt_ctrl->fmt_spatial_dither_frame_counter_bit_swap = 0; + } + + opp->funcs->program_fmt_control(opp, fmt_ctrl); opp->funcs->set_clamping(opp, clamping); } -void vpe10_opp_program_pipe_alpha(struct opp *opp, uint16_t alpha) +void vpe10_opp_program_pipe_control(struct opp *opp, const struct opp_pipe_control_params *params) { PROGRAM_ENTRY(); - REG_UPDATE(VPOPP_PIPE_CONTROL, VPOPP_PIPE_ALPHA, alpha); -} - -void vpe10_opp_program_pipe_bypass(struct opp *opp, bool enable) -{ - PROGRAM_ENTRY(); - REG_UPDATE(VPOPP_PIPE_CONTROL, VPOPP_PIPE_DIGITAL_BYPASS_EN, enable); + REG_SET_2(VPOPP_PIPE_CONTROL, REG_DEFAULT(VPOPP_PIPE_CONTROL), VPOPP_PIPE_ALPHA, params->alpha, + VPOPP_PIPE_DIGITAL_BYPASS_EN, params->bypass_enable); } void vpe10_opp_program_pipe_crc(struct opp *opp, bool enable) { PROGRAM_ENTRY(); - REG_UPDATE(VPOPP_PIPE_CRC_CONTROL, VPOPP_PIPE_CRC_EN, enable); + REG_SET(VPOPP_PIPE_CRC_CONTROL, REG_DEFAULT(VPOPP_PIPE_CRC_CONTROL), VPOPP_PIPE_CRC_EN, enable); } diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c index df0cc313125..98ac68b977e 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c @@ -895,12 +895,9 @@ int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uin dpp->funcs->program_input_transfer_func(dpp, stream_ctx->input_tf); dpp->funcs->program_gamut_remap(dpp, stream_ctx->gamut_remap); - enum mpcc_blend_mode blend_mode = get_blend_mode( - MPC_MUX_TOPSEL_DPP0, MPC_MUX_BOTSEL_DISABLE, vpe_priv->init.debug.mpc_bypass == 1); - // for not bypass mode, we always are in single layer coming from DPP and output to OPP mpc->funcs->program_mpcc_mux(mpc, MPC_MPCCID_0, MPC_MUX_TOPSEL_DPP0, MPC_MUX_BOTSEL_DISABLE, - MPC_MUX_OUTMUX_MPCC0, MPC_MUX_OPPID_OPP0, blend_mode); + MPC_MUX_OUTMUX_MPCC0, MPC_MUX_OPPID_OPP0); // program shaper, 3dlut and 1dlut in MPC for stream before blend mpc->funcs->program_movable_cm( @@ -933,7 +930,11 @@ int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uin config_writer_complete(&vpe_priv->config_writer); } - vpe10_create_stream_ops_config(vpe_priv, pipe_idx, stream_ctx, cmd_input, cmd_info->ops); + enum mpcc_blend_mode blend_mode = get_blend_mode( + MPC_MUX_TOPSEL_DPP0, MPC_MUX_BOTSEL_DISABLE, vpe_priv->init.debug.mpc_bypass == 1); + + vpe10_create_stream_ops_config( + vpe_priv, pipe_idx, stream_ctx, cmd_input, cmd_info->ops, blend_mode); /* start segment specific programming */ vpe_priv->fe_cb_ctx.stream_sharing = false; @@ -962,9 +963,11 @@ int32_t vpe10_program_backend( struct bit_depth_reduction_params fmt_bit_depth; struct clamping_and_pixel_encoding_params clamp_param; + struct opp_pipe_control_params pipe_ctrl_param; enum color_depth display_color_depth; uint16_t alpha_16; bool opp_dig_bypass = false; + struct fmt_control_params fmt_ctrl = {0}; vpe_priv->be_cb_ctx.vpe_priv = vpe_priv; config_writer_set_callback( @@ -1007,8 +1010,9 @@ int32_t vpe10_program_backend( alpha_16 = 0xffff; } - opp->funcs->program_pipe_alpha(opp, alpha_16); - opp->funcs->program_pipe_bypass(opp, opp_dig_bypass); + pipe_ctrl_param.alpha = alpha_16; + pipe_ctrl_param.bypass_enable = opp_dig_bypass; + opp->funcs->program_pipe_control(opp, &pipe_ctrl_param); display_color_depth = vpe_get_color_depth(surface_info->format); build_clamping_params(opp, &clamp_param); @@ -1016,7 +1020,7 @@ int32_t vpe10_program_backend( // disable dynamic expansion for now as no use case opp->funcs->set_dyn_expansion(opp, false, display_color_depth); - opp->funcs->program_fmt(opp, &fmt_bit_depth, &clamp_param); + opp->funcs->program_fmt(opp, &fmt_bit_depth, &fmt_ctrl, &clamp_param); if (vpe_priv->init.debug.opp_pipe_crc_ctrl) opp->funcs->program_pipe_crc(opp, true); @@ -1077,7 +1081,8 @@ enum vpe_status vpe10_populate_cmd_info(struct vpe_priv *vpe_priv) } void vpe10_create_stream_ops_config(struct vpe_priv *vpe_priv, uint32_t pipe_idx, - struct stream_ctx *stream_ctx, struct vpe_cmd_input *cmd_input, enum vpe_cmd_ops ops) + struct stream_ctx *stream_ctx, struct vpe_cmd_input *cmd_input, enum vpe_cmd_ops ops, + enum mpcc_blend_mode blend_mode) { /* put all hw programming that can be shared according to the cmd type within a stream here */ struct mpcc_blnd_cfg blndcfg = {0}; @@ -1185,6 +1190,7 @@ void vpe10_create_stream_ops_config(struct vpe_priv *vpe_priv, uint32_t pipe_idx blndcfg.top_gain = 0x1f000; blndcfg.bottom_inside_gain = 0x1f000; blndcfg.bottom_outside_gain = 0x1f000; + blndcfg.blend_mode = blend_mode; mpc->funcs->program_mpcc_blending(mpc, MPC_MPCCID_0, &blndcfg); diff --git a/src/amd/vpelib/src/core/inc/mpc.h b/src/amd/vpelib/src/core/inc/mpc.h index 1ef35f78310..bfc140774da 100644 --- a/src/amd/vpelib/src/core/inc/mpc.h +++ b/src/amd/vpelib/src/core/inc/mpc.h @@ -91,6 +91,8 @@ struct mpcc_blnd_cfg { int top_gain; int bottom_inside_gain; int bottom_outside_gain; + + enum mpcc_blend_mode blend_mode; }; enum mpc_output_csc_mode { @@ -109,8 +111,7 @@ struct mpc_denorm_clamp { struct mpc_funcs { void (*program_mpcc_mux)(struct mpc *mpc, enum mpc_mpccid mpcc_idx, enum mpc_mux_topsel topsel, - enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, enum mpc_mux_oppid oppid, - enum mpcc_blend_mode blend_mode); + enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, enum mpc_mux_oppid oppid); void (*program_mpcc_blending)( struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg); diff --git a/src/amd/vpelib/src/core/inc/opp.h b/src/amd/vpelib/src/core/inc/opp.h index 69809db666d..bd246cfae3e 100644 --- a/src/amd/vpelib/src/core/inc/opp.h +++ b/src/amd/vpelib/src/core/inc/opp.h @@ -97,25 +97,36 @@ struct bit_depth_reduction_params { // enum vpe_pixel_encoding pixel_encoding; // not used and not initialized yet }; +struct opp_pipe_control_params { + /**< pipe alpha */ + uint16_t alpha; + /**< Digital bypass enable */ + bool bypass_enable; + /**< Enable bypass mode for the pipe */ +}; + +struct fmt_control_params { + uint8_t fmt_spatial_dither_frame_counter_max; + uint8_t fmt_spatial_dither_frame_counter_bit_swap; + +}; + struct opp_funcs { void (*set_clamping)(struct opp *opp, const struct clamping_and_pixel_encoding_params *params); void (*set_dyn_expansion)(struct opp *opp, bool enable, enum color_depth color_dpth); - void (*set_truncation)(struct opp *opp, const struct bit_depth_reduction_params *params); - - void (*set_spatial_dither)(struct opp *opp, const struct bit_depth_reduction_params *params); - void (*program_bit_depth_reduction)( struct opp *opp, const struct bit_depth_reduction_params *params); void (*program_fmt)(struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth, - struct clamping_and_pixel_encoding_params *clamping); + struct fmt_control_params *fmt_ctrl, struct clamping_and_pixel_encoding_params *clamping); - void (*program_pipe_alpha)(struct opp *opp, uint16_t alpha); + void (*program_fmt_control)(struct opp *opp, struct fmt_control_params *fmt_ctrl); + + void (*program_pipe_control)(struct opp *opp, const struct opp_pipe_control_params *params); - void (*program_pipe_bypass)(struct opp *opp, bool enable); void (*program_pipe_crc)(struct opp *opp, bool enable); }; diff --git a/src/amd/vpelib/src/core/inc/reg_helper.h b/src/amd/vpelib/src/core/inc/reg_helper.h index 036affed1ad..5400b82bca9 100644 --- a/src/amd/vpelib/src/core/inc/reg_helper.h +++ b/src/amd/vpelib/src/core/inc/reg_helper.h @@ -231,33 +231,6 @@ typedef struct reg_id_val { config_writer_fill_direct_config_packet(config_writer, &packet); \ } while (0) -#define REG_UPDATE(reg, field, val) REG_SET(reg, REG_CURRENT(reg), field, val) -#define REG_UPDATE_2(reg, f1, v1, f2, v2) REG_SET_2(reg, REG_CURRENT(reg), f1, v1, f2, v2) -#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ - REG_SET_3(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3) -#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ - REG_SET_4(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4) -#define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - REG_SET_5(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) - -#define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - REG_SET_6(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) - -#define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - REG_SET_7(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) - -#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - REG_SET_8(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) - -#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ - REG_SET_9(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, \ - v8, f9, v9) - -#define REG_UPDATE_10( \ - reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ - REG_SET_10(reg, REG_CURRENT(reg), f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, \ - v8, f9, v9, f10, v10) - #define REG_SET_DEFAULT(reg_name) \ do { \ packet.bits.INC = 0; \