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radv: remove useless sync after CmdClear{Color,DepthStencil}Image()

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'post_flush' is only set to NULL for the normal clear path
(ie. only vkCmdClearColorImage() and vkCmdClearDepthStencilImage()
are affected commands).

Because these two operations have to be externally synchronized
with VK_PIPELINE_STAGE_TRANSFER_BIT and VK_ACCESS_TRANSFER_WRITE_BIT,
it's useless to set those flags internallY.

VK_PIPELINE_STAGE_TRANSFER_BIT will wait for compute to be idle,
while VK_ACCESS_TRANSFER_WRITE_BIT will invalidate both L1 vector
caches and L2. RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 will be superseded
by RADV_CMD_FLAG_INV_GLOBAL_L2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2018-11-21 11:34:42 +01:00
parent 33b2f74e77
commit 4ff4af3d91
1 changed files with 0 additions and 4 deletions
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4
src/amd/vulkan/radv_meta_clear.c
View file

@ -969,8 +969,6 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
if (post_flush) {
*post_flush |= flush_bits;
} else {
cmd_buffer->state.flush_bits |= flush_bits;
}
return true;
@ -1453,8 +1451,6 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
if (post_flush) {
*post_flush |= flush_bits;
} else {
cmd_buffer->state.flush_bits |= flush_bits;
}
radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,