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radeonsi: use the optimal packet order before draw packets for VS flushes too

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
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Marek Olšák 2021-03-21 15:18:52 -04:00 • committed by Marge Bot
parent b1a73ec99b
commit 4fb1b7b2d8
1 changed files with 2 additions and 1 deletions
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3
src/gallium/drivers/radeonsi/si_state_draw.cpp
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@ -2085,7 +2085,8 @@ static void si_draw_vbo(struct pipe_context *ctx,
/* Use optimal packet order based on whether we need to sync the pipeline. */
if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB |
SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH))) {
SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_VS_PARTIAL_FLUSH))) {
/* If we have to wait for idle, set all states first, so that all
* SET packets are processed in parallel with previous draw calls.
* Then draw and prefetch at the end. This ensures that the time