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intel: move internal shader compile to vtn_bindgen2

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33329>
This commit is contained in:
Lionel Landwerlin 2025-01-30 21:32:47 +02:00 • committed by Marge Bot
parent fdeb05c907
commit 4f9eace864
8 changed files with 16 additions and 147 deletions
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15
src/gallium/drivers/iris/iris_indirect_gen.c
View file

@ -44,25 +44,18 @@
#include "libintel_shaders.h"
#if GFX_VERx10 == 80
# include "intel_gfx80_shaders_spv.h"
# include "intel_gfx80_shaders_binding.h"
#elif GFX_VERx10 == 90
# include "intel_gfx90_shaders_spv.h"
# include "intel_gfx90_shaders_binding.h"
#elif GFX_VERx10 == 110
# include "intel_gfx110_shaders_spv.h"
# include "intel_gfx110_shaders_binding.h"
#elif GFX_VERx10 == 120
# include "intel_gfx120_shaders_spv.h"
# include "intel_gfx120_shaders_binding.h"
#elif GFX_VERx10 == 125
# include "intel_gfx125_shaders_spv.h"
# include "intel_gfx125_shaders_binding.h"
#elif GFX_VERx10 == 200
# include "intel_gfx200_shaders_spv.h"
# include "intel_gfx200_shaders_binding.h"
#elif GFX_VERx10 == 300
# include "intel_gfx300_shaders_spv.h"
# include "intel_gfx300_shaders_binding.h"
#else
# error "Unsupported generation"
@ -82,13 +75,6 @@ load_fragment_index(nir_builder *b)
nir_channel(b, pos_in, 0));
}
static const uint32_t *
load_shader_lib_spv(uint32_t *out_size)
{
*out_size = sizeof(genX(shaders_spv));
return genX(shaders_spv);
}
static unsigned
iris_call_generation_shader(struct iris_screen *screen, nir_builder *b)
{
@ -112,7 +98,6 @@ iris_call_generation_shader(struct iris_screen *screen, nir_builder *b)
void
genX(init_screen_gen_state)(struct iris_screen *screen)
{
screen->vtbl.load_shader_lib_spv = load_shader_lib_spv;
screen->vtbl.call_generation_shader = iris_call_generation_shader;
}

25
src/gallium/drivers/iris/iris_program_cache.c
View file

@ -338,26 +338,6 @@ iris_destroy_program_cache(struct iris_context *ice)
ralloc_free(ice->shaders.cache);
}
static void
link_libintel_shaders(nir_shader *nir,
const uint32_t *spv_code, uint32_t spv_size)
{
nir_shader *libintel = brw_nir_from_spirv(nir, spv_code, spv_size);
nir_link_shader_functions(nir, libintel);
NIR_PASS_V(nir, nir_inline_functions);
NIR_PASS_V(nir, nir_remove_non_entrypoints);
NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_function_temp,
glsl_get_cl_type_size_align);
NIR_PASS_V(nir, nir_opt_deref);
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
NIR_PASS_V(nir, nir_lower_explicit_io,
nir_var_shader_temp | nir_var_function_temp | nir_var_mem_shared |
nir_var_mem_global,
nir_address_format_62bit_generic);
NIR_PASS_V(nir, nir_lower_scratch_to_var);
}
void
iris_ensure_indirect_generation_shader(struct iris_batch *batch)
{
@ -389,13 +369,8 @@ iris_ensure_indirect_generation_shader(struct iris_batch *batch)
uint32_t uniform_size =
screen->vtbl.call_generation_shader(screen, &b);
uint32_t spv_size;
const uint32_t *spv_code = screen->vtbl.load_shader_lib_spv(&spv_size);
nir_shader *nir = b.shader;
link_libintel_shaders(nir, spv_code, spv_size);
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
NIR_PASS_V(nir, nir_opt_cse);
NIR_PASS_V(nir, nir_opt_gcm, true);

1
src/gallium/drivers/iris/iris_screen.h
View file

@ -159,7 +159,6 @@ struct iris_vtable {
void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
void (*disable_rhwo_optimization)(struct iris_batch *batch, bool disable);
const uint32_t *(*load_shader_lib_spv)(uint32_t *out_size);
unsigned (*call_generation_shader)(struct iris_screen *screen, nir_builder *b);
};

29
src/intel/shaders/meson.build
View file

@ -36,6 +36,7 @@ intel_shaders_gens = [ [ 80, 8],
[200, 20],
[300, 30] ]
intel_shaders = []
intel_shaders_headers = []
foreach gen : intel_shaders_gens
intel_shaders_spv = custom_target(
input : intel_shader_files,
@ -55,23 +56,25 @@ foreach gen : intel_shaders_gens
depends : [gen_cl_xml_pack, intel_dev_wa_src],
)
intel_shaders += custom_target(
input : ['spv2hex.py', intel_shaders_spv],
output : 'intel_gfx@0@_shaders_spv.h'.format(gen[0]),
command : [
prog_python, '@INPUT@', '--output', '@OUTPUT@',
'--prefix', 'gfx@0@_shaders_spv'.format(gen[1]),
],
_intel_shaders = custom_target(
input : intel_shaders_spv,
output : ['intel_gfx@0@_shaders_binding.cpp'.format(gen[0]),
'intel_gfx@0@_shaders_binding.h'.format(gen[0])],
command : [prog_vtn_bindgen2, intel_shaders_spv, '@OUTPUT0@', '@OUTPUT1@'],
)
intel_shaders += custom_target(
input : intel_shaders_spv,
output : 'intel_gfx@0@_shaders_binding.h'.format(gen[0]),
command : [prog_vtn_bindgen, intel_shaders_spv, '@OUTPUT@'],
)
intel_shaders += _intel_shaders
intel_shaders_headers += _intel_shaders[1]
endforeach
libintel_shaders = static_library(
'intel_shaders',
intel_shaders,
dependencies : idep_nir,
)
idep_intel_shaders = declare_dependency(
sources : intel_shaders,
link_with : libintel_shaders,
sources : intel_shaders_headers,
include_directories : include_directories('.'),
)

43
src/intel/shaders/spv2hex.py
View file

@ -1,43 +0,0 @@
#!/usr/bin/env python3
# Copyright © 2025 Intel Corporation
# SPDX-License-Identifier: MIT
from __future__ import annotations
import argparse
import binascii
def main() -> None:
p = argparse.ArgumentParser()
p.add_argument('--output', dest='output', action='store',
help='Output file', required=True)
p.add_argument('--prefix', action='store',
help='Prefix string to use', required=True)
p.add_argument('inputs', metavar='SPIRV', nargs='+')
args = p.parse_args()
for f in args.inputs:
with open(f, 'rb') as fin:
with open(args.output, 'w') as fout:
fout.write("#pragma one\n")
fout.write("const uint32_t {0}[] = {{".format(args.prefix))
count = 0
while True:
dword = fin.read(4)
if not dword:
break
if count % 8 == 0:
fout.write("\n ")
fout.write('{:#x}, '.format(int.from_bytes(dword, byteorder='little', signed=False)))
count += 1
fout.write("\n")
fout.write("};\n")
if __name__ == '__main__':
main()

2
src/intel/vulkan/anv_genX.h
View file

@ -52,8 +52,6 @@ VkResult genX(init_device_state)(struct anv_device *device);
void genX(init_cps_device_state)(struct anv_device *device);
const uint32_t *genX(libanv_spv)(uint32_t *out_size);
uint32_t genX(call_internal_shader)(nir_builder *b,
enum anv_internal_kernel_name shader_name);

35
src/intel/vulkan/anv_internal_kernels.c
View file

@ -48,37 +48,8 @@ lower_base_workgroup_id(nir_builder *b, nir_intrinsic_instr *intrin,
return true;
}
static nir_shader *
load_libanv(struct anv_device *device)
{
uint32_t spv_size;
const uint32_t *spv_code = anv_genX(device->info, libanv_spv)(&spv_size);
void *mem_ctx = ralloc_context(NULL);
return brw_nir_from_spirv(mem_ctx, spv_code, spv_size);
}
static void
link_libanv(nir_shader *nir, const nir_shader *libanv)
{
nir_link_shader_functions(nir, libanv);
NIR_PASS_V(nir, nir_inline_functions);
NIR_PASS_V(nir, nir_remove_non_entrypoints);
NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_function_temp,
glsl_get_cl_type_size_align);
NIR_PASS_V(nir, nir_opt_deref);
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
NIR_PASS_V(nir, nir_lower_explicit_io,
nir_var_shader_temp | nir_var_function_temp | nir_var_mem_shared |
nir_var_mem_global,
nir_address_format_62bit_generic);
NIR_PASS_V(nir, nir_lower_scratch_to_var);
}
static struct anv_shader_bin *
compile_shader(struct anv_device *device,
const nir_shader *libanv,
enum anv_internal_kernel_name shader_name,
gl_shader_stage stage,
const char *name,
@ -97,8 +68,6 @@ compile_shader(struct anv_device *device,
nir_shader *nir = b.shader;
link_libanv(nir, libanv);
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
NIR_PASS_V(nir, nir_opt_cse);
NIR_PASS_V(nir, nir_opt_gcm, true);
@ -349,17 +318,13 @@ anv_device_get_internal_shader(struct anv_device *device,
return VK_SUCCESS;
}
nir_shader *libanv_shaders = load_libanv(device);
bin = compile_shader(device,
libanv_shaders,
name,
internal_kernels[name].stage,
internal_kernels[name].key.name,
&internal_kernels[name].key,
sizeof(internal_kernels[name].key),
internal_kernels[name].send_count);
ralloc_free(libanv_shaders);
if (bin == NULL)
return vk_errorf(device, VK_ERROR_OUT_OF_HOST_MEMORY,
"Unable to compiler internal kernel");

13
src/intel/vulkan/genX_internal_kernels.c
View file

@ -9,22 +9,16 @@
#include "compiler/nir/nir_serialize.h"
#if GFX_VERx10 == 90
# include "intel_gfx90_shaders_spv.h"
# include "intel_gfx90_shaders_binding.h"
#elif GFX_VERx10 == 110
# include "intel_gfx110_shaders_spv.h"
# include "intel_gfx110_shaders_binding.h"
#elif GFX_VERx10 == 120
# include "intel_gfx120_shaders_spv.h"
# include "intel_gfx120_shaders_binding.h"
#elif GFX_VERx10 == 125
# include "intel_gfx125_shaders_spv.h"
# include "intel_gfx125_shaders_binding.h"
#elif GFX_VERx10 == 200
# include "intel_gfx200_shaders_spv.h"
# include "intel_gfx200_shaders_binding.h"
#elif GFX_VERx10 == 300
# include "intel_gfx300_shaders_spv.h"
# include "intel_gfx300_shaders_binding.h"
#else
# error "Unsupported generation"
@ -37,13 +31,6 @@
.base = offsetof(struct_name, field_name), \
.range = bit_size / 8)
const uint32_t *
genX(libanv_spv)(uint32_t *out_size)
{
*out_size = sizeof(genX(shaders_spv));
return genX(shaders_spv);
}
static nir_def *
load_fragment_index(nir_builder *b)
{