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radv: move emission of two PA_SC_* registers to the pipeline CS

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They don't have to be updated dynamically.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-12-06 12:12:38 +01:00
parent 87f7ec8a2c
commit 4f659224c8
2 changed files with 3 additions and 4 deletions
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5
src/amd/vulkan/radv_cmd_buffer.c
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@ -874,12 +874,9 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
return;
radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
radeon_set_context_reg_seq(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, 1);
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
/* GFX9: Flush DFSM when the AA mode changes. */

2
src/amd/vulkan/radv_pipeline.c
View file

@ -3648,7 +3648,9 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
/* The exclusion bits can be set to improve rasterization efficiency
* if no sample lies on the pixel boundary (-8 sample offset). It's