From 4f5edcd0eec034b4806a3fc025567acc61ea5177 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Fri, 19 May 2023 15:29:19 -0700 Subject: [PATCH] amd/drm-shim: add raven2 It differs from raven in interesting ways (e.g., GB_ADDR_CONFIG). Part-of: --- src/amd/drm-shim/amdgpu_devices.c | 129 ++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/src/amd/drm-shim/amdgpu_devices.c b/src/amd/drm-shim/amdgpu_devices.c index 315015fabac..c99bddfb89d 100644 --- a/src/amd/drm-shim/amdgpu_devices.c +++ b/src/amd/drm-shim/amdgpu_devices.c @@ -170,6 +170,135 @@ const struct amdgpu_device amdgpu_devices[] = { }, }, }, + { + .name = "raven2", + .radeon_family = CHIP_RAVEN2, + .hw_ip_gfx = { + .hw_ip_version_major = 9, + .hw_ip_version_minor = 0, + .capabilities_flags = 0llu, + .ib_start_alignment = 32, + .ib_size_alignment = 32, + .available_rings = 0x1, + .ip_discovery_version = 0x0000, + }, + .hw_ip_compute = { + .hw_ip_version_major = 9, + .hw_ip_version_minor = 0, + .capabilities_flags = 0llu, + .ib_start_alignment = 32, + .ib_size_alignment = 32, + .available_rings = 0xf, + .ip_discovery_version = 0x0000, + }, + .fw_gfx_me = { + .ver = 166, + .feature = 53, + }, + .fw_gfx_pfp = { + .ver = 194, + .feature = 53, + }, + .fw_gfx_mec = { + .ver = 464, + .feature = 53, + }, + .mmr_regs = { + 0x263e, 0xffffffff, 0x26013041, + }, + .mmr_reg_count = 1, + .dev = { + .device_id = 0x15d8, + .chip_rev = 0x09, + .external_rev = 0x82, + .pci_rev = 0xea, + .family = AMDGPU_FAMILY_RV, + .num_shader_engines = 1, + .num_shader_arrays_per_engine = 1, + .gpu_counter_freq = 100000, + .max_engine_clock = 600000llu, + .max_memory_clock = 800000llu, + .cu_active_number = 3, + .cu_ao_mask = 0x7, + .cu_bitmap = { + { 0x7, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + }, + .enabled_rb_pipes_mask = 0x1, + .num_rb_pipes = 1, + .num_hw_gfx_contexts = 8, + .pcie_gen = 0, + .ids_flags = 0x1llu, + .virtual_address_offset = 0x200000llu, + .virtual_address_max = 0x800000000000llu, + .virtual_address_alignment = 4096, + .pte_fragment_size = 2097152, + .gart_page_size = 4096, + .ce_ram_size = 32768, + .vram_type = 8, + .vram_bit_width = 64, + .vce_harvest_config = 0, + .gc_double_offchip_lds_buf = 1, + .prim_buf_gpu_addr = 0llu, + .pos_buf_gpu_addr = 0llu, + .cntl_sb_buf_gpu_addr = 0llu, + .param_buf_gpu_addr = 0llu, + .prim_buf_size = 0, + .pos_buf_size = 0, + .cntl_sb_buf_size = 0, + .param_buf_size = 0, + .wave_front_size = 64, + .num_shader_visible_vgprs = 256, + .num_cu_per_sh = 3, + .num_tcc_blocks = 2, + .gs_vgt_table_depth = 32, + .gs_prim_buffer_depth = 1792, + .max_gs_waves_per_vgt = 32, + .pcie_num_lanes = 0, + .cu_ao_bitmap = { + { 0x7, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + }, + .high_va_offset = 0xffff800000000000llu, + .high_va_max = 0xffffffffffe00000llu, + .pa_sc_tile_steering_override = 0, + .tcc_disabled_mask = 0llu, + .min_engine_clock = 0llu, + .min_memory_clock = 0llu, + .tcp_cache_size = 0, + .num_sqc_per_wgp = 0, + .sqc_data_cache_size = 0, + .sqc_inst_cache_size = 0, + .gl1c_cache_size = 0, + .gl2c_cache_size = 0, + .mall_size = 0llu, + .enabled_rb_pipes_mask_hi = 0, + }, + .mem = { + .vram = { + .total_heap_size = 67108864, + .usable_heap_size = 50491392, + .heap_usage = 51437568, + .max_allocation = 37868544, + }, + .cpu_accessible_vram = { + .total_heap_size = 67108864, + .usable_heap_size = 50491392, + .heap_usage = 51437568, + .max_allocation = 37868544, + }, + .gtt = { + .total_heap_size = 3057070080, + .usable_heap_size = 3052445696, + .heap_usage = 62390272, + .max_allocation = 2289334272, + }, + }, + }, { .name = "stoney", .radeon_family = CHIP_STONEY,