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kraid: RA per-byte
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42200>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
4ed955b7f8
commit
4f1c72e665
3 changed files with 144 additions and 41 deletions
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@ -111,6 +111,10 @@ impl From<&SmallConstant> for FAURef {
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/// write is simply masked.
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#[derive(Clone, Copy, PartialEq)]
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pub enum RegRange {
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Byte0,
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Byte1,
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Byte2,
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Byte3,
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Half0,
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Half1,
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Regs(u8),
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@ -125,6 +129,10 @@ pub struct RegRef {
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impl fmt::Display for RegRef {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match &self.range {
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RegRange::Byte0 => write!(f, "r{}.b0", self.idx),
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RegRange::Byte1 => write!(f, "r{}.b1", self.idx),
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RegRange::Byte2 => write!(f, "r{}.b2", self.idx),
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RegRange::Byte3 => write!(f, "r{}.b3", self.idx),
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RegRange::Half0 => write!(f, "r{}.h0", self.idx),
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RegRange::Half1 => write!(f, "r{}.h1", self.idx),
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RegRange::Regs(n) => {
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@ -141,6 +149,10 @@ impl fmt::Display for RegRef {
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impl RegRef {
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pub fn bytes(&self) -> u8 {
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match self.range {
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RegRange::Byte0
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| RegRange::Byte1
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| RegRange::Byte2
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| RegRange::Byte3 => 1,
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RegRange::Half0 | RegRange::Half1 => 2,
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RegRange::Regs(n) => n * 4,
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}
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@ -148,8 +160,10 @@ impl RegRef {
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pub fn byte_offset(&self) -> u8 {
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match self.range {
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RegRange::Half0 | RegRange::Regs(_) => 0,
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RegRange::Half1 => 2,
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RegRange::Byte0 | RegRange::Half0 | RegRange::Regs(_) => 0,
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RegRange::Byte1 => 1,
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RegRange::Byte2 | RegRange::Half1 => 2,
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RegRange::Byte3 => 3,
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}
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}
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}
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@ -553,6 +567,10 @@ impl fmt::Display for DstLanes {
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impl From<RegRange> for DstLanes {
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fn from(range: RegRange) -> DstLanes {
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match range {
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RegRange::Byte0 => DstLanes::B0,
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RegRange::Byte1 => DstLanes::B1,
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RegRange::Byte2 => DstLanes::B2,
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RegRange::Byte3 => DstLanes::B3,
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RegRange::Half0 => DstLanes::H0,
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RegRange::Half1 => DstLanes::H1,
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RegRange::Regs(_) => DstLanes::All,
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@ -3,6 +3,7 @@
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use crate::ir::*;
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use compiler::bitset::*;
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use compiler::smallvec::*;
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use rustc_hash::FxHashMap;
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struct BlockIp {
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@ -82,22 +83,41 @@ impl TrivialLiveness {
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}
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}
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fn reg_ref_for_hr(hr: u8, bytes: u8) -> RegRef {
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let range = if bytes == 2 {
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if hr & 1 == 0 {
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fn widen_lanes(lanes: DstLanes) -> DstLanes {
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use DstLanes::*;
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match lanes {
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None => AnyB,
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All => panic!("Everything supports ALL"),
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AnyB => AnyH,
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AnyH | H0 | H1 => All,
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B0 | B1 => H0,
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B2 | B3 => H1,
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}
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}
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fn reg_ref_for_byte(b: u8, bytes: u8) -> RegRef {
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let range = if bytes >= 4 {
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assert_eq!(bytes % 4, 0);
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RegRange::Regs((bytes / 4).try_into().unwrap())
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} else if bytes == 2 {
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assert_eq!(b % 2, 0);
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if b % 4 == 0 {
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RegRange::Half0
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} else {
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RegRange::Half1
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}
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} else {
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assert_eq!(bytes % 4, 0);
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RegRange::Regs(bytes / 4)
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assert_eq!(bytes, 1);
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match b % 4 {
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0 => RegRange::Byte0,
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1 => RegRange::Byte1,
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2 => RegRange::Byte2,
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3 => RegRange::Byte3,
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_ => panic!("bytes % 4 < 4"),
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}
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};
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RegRef {
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idx: hr >> 1,
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range,
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}
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RegRef { idx: b / 4, range }
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}
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fn ra_trivial(s: &mut Shader) {
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@ -105,8 +125,8 @@ fn ra_trivial(s: &mut Shader) {
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// Allocate in units of half registers. We might be a dumb allocator but
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// we can at least try to exercise Kraid's half register model.
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let mut hr_used: BitSet = Default::default();
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let mut ssa_hr: FxHashMap<SSAValue, u8> = Default::default();
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let mut byte_used: BitSet = Default::default();
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let mut ssa_b: FxHashMap<SSAValue, u8> = Default::default();
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for (bi, block) in s.blocks.iter_mut().enumerate() {
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for (ip, instr) in block.instrs.iter_mut().enumerate() {
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@ -115,27 +135,31 @@ fn ra_trivial(s: &mut Shader) {
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continue;
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};
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let mut vec_hr = 0;
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let mut vec_b = 0;
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for (i, ssa) in vec.iter().enumerate() {
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let hr = *ssa_hr.get(ssa).unwrap();
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let b = *ssa_b.get(ssa).unwrap();
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if live.is_killed_by(ssa, bi, ip) {
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let hr_count = ssa.bits().div_ceil(16);
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for hr in hr..(hr + hr_count) {
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hr_used.remove(hr.into());
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let bytes = ssa.bits() / 8;
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for b in b..(b + bytes) {
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byte_used.remove(b.into());
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}
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}
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if i == 0 {
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vec_hr = hr;
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vec_b = b;
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} else {
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// We don't know how to move registers
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assert_eq!(hr, vec_hr + u8::try_from(i * 2).unwrap());
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assert_eq!(b, vec_b + u8::try_from(i * 4).unwrap());
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}
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}
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let reg = reg_ref_for_hr(vec_hr, vec.bytes());
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let reg = reg_ref_for_byte(vec_b, vec.bytes());
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let swz = match reg.range {
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RegRange::Byte0 => Swizzle::B0000,
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RegRange::Byte1 => Swizzle::B1111,
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RegRange::Byte2 => Swizzle::B2222,
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RegRange::Byte3 => Swizzle::B3333,
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RegRange::Half0 => Swizzle::H00,
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RegRange::Half1 => Swizzle::H11,
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RegRange::Regs(_) => Swizzle::NONE,
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@ -146,33 +170,82 @@ fn ra_trivial(s: &mut Shader) {
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src.src_ref = reg.into();
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}
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for dst in instr.dsts_mut() {
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let mut dst_regs = SmallVec::new();
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for dst in instr.dsts() {
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let DstRef::SSA(vec) = &dst.dst_ref else {
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continue;
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};
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let hr_count = vec.bytes().div_ceil(2);
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let hr_align = hr_count.next_power_of_two();
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let vec_hr = hr_used.find_aligned_unset_range(
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0, // start_point
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hr_count.into(),
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hr_align.into(),
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0, // align_offset
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);
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let mut alloc_lanes = dst.lanes;
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while !s.model.op_dst_supports_lanes(&instr.op, alloc_lanes) {
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alloc_lanes = widen_lanes(alloc_lanes);
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}
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assert!(vec_hr <= 128, "Ran out of registers!");
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let vec_hr = vec_hr as u8;
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let bytes = vec.bytes();
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let alloc_bytes = alloc_lanes.bytes(bytes);
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let (align_mul, align_off) = if bytes > 4 {
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debug_assert_eq!(alloc_lanes, DstLanes::All);
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(bytes.next_power_of_two(), 0)
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} else {
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alloc_lanes.align()
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};
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let mut alloc_start = 0;
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let (b, reg) = loop {
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let b = byte_used.find_aligned_unset_range(
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alloc_start,
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alloc_bytes.into(),
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align_mul.into(),
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align_off.into(),
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);
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assert!(
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b + usize::from(bytes) <= 256,
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"Ran out of registers!"
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);
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let b = b as u8;
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let reg = reg_ref_for_byte(b, alloc_bytes);
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let lanes = DstLanes::from(reg.range);
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match alloc_lanes {
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DstLanes::All => debug_assert_eq!(lanes, DstLanes::All),
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DstLanes::AnyB => debug_assert!(lanes.is_byte()),
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DstLanes::AnyH => debug_assert!(lanes.is_half()),
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_ => debug_assert_eq!(lanes, alloc_lanes),
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}
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if s.model.op_dst_supports_lanes(&instr.op, lanes) {
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break (b, reg);
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}
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alloc_start = usize::from(b) + 1;
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};
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// In case when the SSA value is smaller than the region we
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// just allocated, adjust accordingly.
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let (dst_mul, dst_off) = dst.lanes.align();
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let b = (b & !(dst_mul - 1)) | dst_off;
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for (i, ssa) in vec.iter().enumerate() {
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let hr = vec_hr + u8::try_from(i * 2).unwrap();
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ssa_hr.insert(*ssa, hr);
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ssa_b.insert(*ssa, b + u8::try_from(i * 4).unwrap());
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}
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for hr in vec_hr..(vec_hr + hr_count) {
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hr_used.insert(hr.into());
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// In case when the SSA value is smaller than the region we
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// just allocated, this only marks the bytes consumed by the
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// SSA value as used. This effectively kills the other bytes
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// immediately.
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for i in 0..bytes {
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byte_used.insert(usize::from(b) + usize::from(i));
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}
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*dst = reg_ref_for_hr(vec_hr, vec.bytes()).into();
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dst_regs.push(reg);
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}
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debug_assert_eq!(instr.dsts().len(), dst_regs.len());
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for (dst, reg) in
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instr.dsts_mut().iter_mut().zip(dst_regs.into_iter())
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{
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*dst = reg.into();
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}
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for dst in instr.dsts() {
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@ -182,10 +255,10 @@ fn ra_trivial(s: &mut Shader) {
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for ssa in vec {
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if live.is_never_used(ssa) {
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let first_hr = *ssa_hr.get(ssa).unwrap();
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let hr_count = ssa.bits().div_ceil(16);
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for hr in first_hr..(first_hr + hr_count) {
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hr_used.remove(hr.into());
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let vec_b = *ssa_b.get(ssa).unwrap();
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let bytes = ssa.bits() / 8;
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for b in 0..bytes {
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byte_used.insert((vec_b + b).into());
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}
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}
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}
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@ -35,6 +35,18 @@ fn validate_instr(instr: &Instr, ssa_vals: &mut FxHashSet<SSAValue>) {
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}
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}
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SrcRef::Reg(reg) => match reg.range {
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RegRange::Byte0 => {
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assert!(src.swizzle.bytes_read() & !0b0001 == 0);
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}
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RegRange::Byte1 => {
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assert!(src.swizzle.bytes_read() & !0b0010 == 0);
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}
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RegRange::Byte2 => {
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assert!(src.swizzle.bytes_read() & !0b0100 == 0);
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}
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RegRange::Byte3 => {
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assert!(src.swizzle.bytes_read() & !0b1000 == 0);
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}
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RegRange::Half0 => {
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assert!(src.swizzle.bytes_read() & !0b0011 == 0);
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}
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