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i965: Make the brw_inst helpers take a device_info instead of a context

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Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand 2015-04-14 18:00:06 -07:00
parent 6219a8f098
commit 4e9c79c847
16 changed files with 1006 additions and 995 deletions
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21
src/mesa/drivers/dri/i965/brw_clip_line.c
View file

@ -158,9 +158,9 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
if (brw->has_negative_rhw_bug) {
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
}
/* Set the initial vertex source mask: The first 6 planes are the bounds
@ -177,12 +177,12 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
/* if (planemask & 1)
*/
brw_AND(p, v1_null_ud, c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
brw_AND(p, v1_null_ud, c->reg.vertex_src_mask, brw_imm_ud(1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
/* user clip distance: just fetch the correct float from each vertex */
@ -228,7 +228,8 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t1 );
brw_MOV(p, c->reg.t1, c->reg.t);
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
}
brw_ELSE(p);
{
@ -250,7 +251,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
brw_MOV(p, c->reg.t0, c->reg.t);
brw_inst_set_pred_control(brw, brw_last_inst,
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
}
@ -269,14 +270,14 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
/* while (planemask>>=1) != 0
*/
brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
}
brw_WHILE(p);
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_ADD(p, c->reg.t, c->reg.t0, c->reg.t1);
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.t, brw_imm_f(1.0));

45
src/mesa/drivers/dri/i965/brw_clip_tri.c
View file

@ -235,11 +235,10 @@ load_clip_distance(struct brw_clip_compile *c, struct brw_indirect vtx,
struct brw_reg dst, GLuint hpos_offset, int cond)
{
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
dst = vec4(dst);
brw_AND(p, vec1(brw_null_reg()), c->reg.vertex_src_mask, brw_imm_ud(1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
struct brw_indirect temp_ptr = brw_indirect(7, 0);
@ -262,7 +261,6 @@ load_clip_distance(struct brw_clip_compile *c, struct brw_indirect vtx,
void brw_clip_tri( struct brw_clip_compile *c )
{
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
struct brw_indirect vtx = brw_indirect(0, 0);
struct brw_indirect vtxPrev = brw_indirect(1, 0);
struct brw_indirect vtxOut = brw_indirect(2, 0);
@ -296,7 +294,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
/* if (planemask & 1)
*/
brw_AND(p, vec1(brw_null_reg()), c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
@ -339,7 +337,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
*/
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) );
brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtxPrev));
brw_inst_set_pred_control(brw, brw_last_inst,
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
brw_clip_interp_vertex(c, vtxOut, vtxPrev, vtx, c->reg.t, false);
@ -381,7 +379,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
*/
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) );
brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtx));
brw_inst_set_pred_control(brw, brw_last_inst,
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
brw_clip_interp_vertex(c, vtxOut, vtx, vtxPrev, c->reg.t, true);
@ -408,10 +406,10 @@ void brw_clip_tri( struct brw_clip_compile *c )
/* while (--loopcount != 0)
*/
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
/* vtxPrev = *(outlist_ptr-1) OR: outlist[nr_verts-1]
* inlist = outlist
@ -442,7 +440,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
/* && (planemask>>=1) != 0
*/
brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1));
brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float)));
}
@ -455,7 +453,6 @@ void brw_clip_tri( struct brw_clip_compile *c )
void brw_clip_tri_emit_polygon(struct brw_clip_compile *c)
{
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
/* for (loopcount = nr_verts-2; loopcount > 0; loopcount--)
*/
@ -463,7 +460,7 @@ void brw_clip_tri_emit_polygon(struct brw_clip_compile *c)
c->reg.loopcount,
c->reg.nr_verts,
brw_imm_d(-2));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_G);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_G);
brw_IF(p, BRW_EXECUTE_1);
{
@ -489,10 +486,10 @@ void brw_clip_tri_emit_polygon(struct brw_clip_compile *c)
brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_clip_emit_vue(c, v0, BRW_URB_WRITE_EOT_COMPLETE,
((_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT)
@ -537,7 +534,6 @@ static void brw_clip_test( struct brw_clip_compile *c )
struct brw_indirect vt2 = brw_indirect(2, 0);
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */
GLuint hpos_offset = brw_varying_to_offset(&c->vue_map,
@ -563,7 +559,7 @@ static void brw_clip_test( struct brw_clip_compile *c )
brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
brw_OR(p, tmp0, tmp0, get_element(t, 2));
brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
brw_clip_kill_thread(c);
@ -579,15 +575,15 @@ static void brw_clip_test( struct brw_clip_compile *c )
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 0), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<5)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 1), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<3)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 2), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<1)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
/* test farz, xmax, ymax plane */
/* clip.xyz > clip.w */
@ -601,7 +597,7 @@ static void brw_clip_test( struct brw_clip_compile *c )
brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
brw_OR(p, tmp0, tmp0, get_element(t, 2));
brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
brw_clip_kill_thread(c);
@ -617,15 +613,15 @@ static void brw_clip_test( struct brw_clip_compile *c )
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 0), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<4)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 1), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<2)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 2), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<0)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
release_tmps(c);
}
@ -634,7 +630,6 @@ static void brw_clip_test( struct brw_clip_compile *c )
void brw_emit_tri_clip( struct brw_clip_compile *c )
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
brw_clip_tri_init_vertices(c);
brw_clip_init_clipmask(c);
@ -642,10 +637,10 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
/* if -ve rhw workaround bit is set,
do cliptest */
if (brw->has_negative_rhw_bug) {
if (p->devinfo->has_negative_rhw_bug) {
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
brw_clip_test(c);

26
src/mesa/drivers/dri/i965/brw_clip_unfilled.c
View file

@ -193,7 +193,6 @@ static void copy_bfc( struct brw_clip_compile *c )
static void compute_offset( struct brw_clip_compile *c )
{
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
struct brw_reg off = c->reg.offset;
struct brw_reg dir = c->reg.dir;
@ -208,7 +207,7 @@ static void compute_offset( struct brw_clip_compile *c )
brw_SEL(p, vec1(off),
brw_abs(get_element(off, 0)), brw_abs(get_element(off, 1)));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_MUL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_factor));
brw_ADD(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_units));
@ -218,7 +217,6 @@ static void compute_offset( struct brw_clip_compile *c )
static void merge_edgeflags( struct brw_clip_compile *c )
{
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
struct brw_reg tmp0 = get_element_ud(c->reg.tmp0, 0);
brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
@ -234,20 +232,20 @@ static void merge_edgeflags( struct brw_clip_compile *c )
brw_IF(p, BRW_EXECUTE_1);
{
brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_EQ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_EQ);
brw_MOV(p, byte_offset(c->reg.vertex[0],
brw_varying_to_offset(&c->vue_map,
VARYING_SLOT_EDGE)),
brw_imm_f(0));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_EQ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_EQ);
brw_MOV(p, byte_offset(c->reg.vertex[2],
brw_varying_to_offset(&c->vue_map,
VARYING_SLOT_EDGE)),
brw_imm_f(0));
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
}
brw_ENDIF(p);
}
@ -275,7 +273,6 @@ static void emit_lines(struct brw_clip_compile *c,
bool do_offset)
{
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
struct brw_indirect v0 = brw_indirect(0, 0);
struct brw_indirect v1 = brw_indirect(1, 0);
struct brw_indirect v0ptr = brw_indirect(2, 0);
@ -295,10 +292,10 @@ static void emit_lines(struct brw_clip_compile *c,
apply_one_offset(c, v0);
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_G);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_G);
}
brw_WHILE(p);
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
}
/* v1ptr = &inlist[nr_verts]
@ -334,10 +331,10 @@ static void emit_lines(struct brw_clip_compile *c,
brw_ENDIF(p);
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
}
@ -346,7 +343,6 @@ static void emit_points(struct brw_clip_compile *c,
bool do_offset )
{
struct brw_compile *p = &c->func;
const struct brw_context *brw = p->brw;
struct brw_indirect v0 = brw_indirect(0, 0);
struct brw_indirect v0ptr = brw_indirect(2, 0);
@ -378,10 +374,10 @@ static void emit_points(struct brw_clip_compile *c,
brw_ENDIF(p);
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
}

2
src/mesa/drivers/dri/i965/brw_clip_util.c
View file

@ -448,7 +448,7 @@ void brw_clip_ff_sync(struct brw_clip_compile *c)
if (brw->gen == 5) {
brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
brw_IF(p, BRW_EXECUTE_1);
{
brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1));

472
src/mesa/drivers/dri/i965/brw_disasm.c
View file

@ -721,50 +721,51 @@ static int
dest(FILE *file, struct brw_context *brw, brw_inst *inst)
{
int err = 0;
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
if (brw_inst_dst_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
err |= reg(file, brw_inst_dst_reg_file(brw, inst),
brw_inst_dst_da_reg_nr(brw, inst));
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
brw_inst_dst_da_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (brw_inst_dst_da1_subreg_nr(brw, inst))
format(file, ".%ld", brw_inst_dst_da1_subreg_nr(brw, inst) /
reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
if (brw_inst_dst_da1_subreg_nr(devinfo, inst))
format(file, ".%ld", brw_inst_dst_da1_subreg_nr(devinfo, inst) /
reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]);
string(file, "<");
err |= control(file, "horiz stride", horiz_stride,
brw_inst_dst_hstride(brw, inst), NULL);
brw_inst_dst_hstride(devinfo, inst), NULL);
string(file, ">");
err |= control(file, "dest reg encoding", reg_encoding,
brw_inst_dst_reg_type(brw, inst), NULL);
brw_inst_dst_reg_type(devinfo, inst), NULL);
} else {
string(file, "g[a0");
if (brw_inst_dst_ia_subreg_nr(brw, inst))
format(file, ".%ld", brw_inst_dst_ia_subreg_nr(brw, inst) /
reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
if (brw_inst_dst_ia1_addr_imm(brw, inst))
format(file, " %d", brw_inst_dst_ia1_addr_imm(brw, inst));
if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
format(file, ".%ld", brw_inst_dst_ia_subreg_nr(devinfo, inst) /
reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]);
if (brw_inst_dst_ia1_addr_imm(devinfo, inst))
format(file, " %d", brw_inst_dst_ia1_addr_imm(devinfo, inst));
string(file, "]<");
err |= control(file, "horiz stride", horiz_stride,
brw_inst_dst_hstride(brw, inst), NULL);
brw_inst_dst_hstride(devinfo, inst), NULL);
string(file, ">");
err |= control(file, "dest reg encoding", reg_encoding,
brw_inst_dst_reg_type(brw, inst), NULL);
brw_inst_dst_reg_type(devinfo, inst), NULL);
}
} else {
if (brw_inst_dst_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
err |= reg(file, brw_inst_dst_reg_file(brw, inst),
brw_inst_dst_da_reg_nr(brw, inst));
if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
brw_inst_dst_da_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (brw_inst_dst_da16_subreg_nr(brw, inst))
format(file, ".%ld", brw_inst_dst_da16_subreg_nr(brw, inst) /
reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
if (brw_inst_dst_da16_subreg_nr(devinfo, inst))
format(file, ".%ld", brw_inst_dst_da16_subreg_nr(devinfo, inst) /
reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]);
string(file, "<1>");
err |= control(file, "writemask", writemask,
brw_inst_da16_writemask(brw, inst), NULL);
brw_inst_da16_writemask(devinfo, inst), NULL);
err |= control(file, "dest reg encoding", reg_encoding,
brw_inst_dst_reg_type(brw, inst), NULL);
brw_inst_dst_reg_type(devinfo, inst), NULL);
} else {
err = 1;
string(file, "Indirect align16 address mode not supported");
@ -779,22 +780,23 @@ dest_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
{
int err = 0;
uint32_t reg_file;
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
if (brw->gen == 6 && brw_inst_3src_dst_reg_file(brw, inst))
if (brw->gen == 6 && brw_inst_3src_dst_reg_file(devinfo, inst))
reg_file = BRW_MESSAGE_REGISTER_FILE;
else
reg_file = BRW_GENERAL_REGISTER_FILE;
err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(brw, inst));
err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (brw_inst_3src_dst_subreg_nr(brw, inst))
format(file, ".%ld", brw_inst_3src_dst_subreg_nr(brw, inst));
if (brw_inst_3src_dst_subreg_nr(devinfo, inst))
format(file, ".%ld", brw_inst_3src_dst_subreg_nr(devinfo, inst));
string(file, "<1>");
err |= control(file, "writemask", writemask,
brw_inst_3src_dst_writemask(brw, inst), NULL);
brw_inst_3src_dst_writemask(devinfo, inst), NULL);
err |= control(file, "dest reg encoding", three_source_reg_encoding,
brw_inst_3src_dst_type(brw, inst), NULL);
brw_inst_3src_dst_type(devinfo, inst), NULL);
return 0;
}
@ -939,25 +941,26 @@ static int
src0_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
{
int err = 0;
unsigned src0_subreg_nr = brw_inst_3src_src0_subreg_nr(brw, inst);
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
unsigned src0_subreg_nr = brw_inst_3src_src0_subreg_nr(devinfo, inst);
err |= control(file, "negate", m_negate,
brw_inst_3src_src0_negate(brw, inst), NULL);
err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(brw, inst), NULL);
brw_inst_3src_src0_negate(devinfo, inst), NULL);
err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(devinfo, inst), NULL);
err |= reg(file, BRW_GENERAL_REGISTER_FILE,
brw_inst_3src_src0_reg_nr(brw, inst));
brw_inst_3src_src0_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (src0_subreg_nr)
format(file, ".%d", src0_subreg_nr);
if (brw_inst_3src_src0_rep_ctrl(brw, inst))
if (brw_inst_3src_src0_rep_ctrl(devinfo, inst))
string(file, "<0,1,0>");
else
string(file, "<4,4,1>");
err |= src_swizzle(file, brw_inst_3src_src0_swizzle(brw, inst));
err |= src_swizzle(file, brw_inst_3src_src0_swizzle(devinfo, inst));
err |= control(file, "src da16 reg type", three_source_reg_encoding,
brw_inst_3src_src_type(brw, inst), NULL);
brw_inst_3src_src_type(devinfo, inst), NULL);
return err;
}
@ -965,25 +968,26 @@ static int
src1_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
{
int err = 0;
unsigned src1_subreg_nr = brw_inst_3src_src1_subreg_nr(brw, inst);
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
unsigned src1_subreg_nr = brw_inst_3src_src1_subreg_nr(devinfo, inst);
err |= control(file, "negate", m_negate,
brw_inst_3src_src1_negate(brw, inst), NULL);
err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(brw, inst), NULL);
brw_inst_3src_src1_negate(devinfo, inst), NULL);
err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(devinfo, inst), NULL);
err |= reg(file, BRW_GENERAL_REGISTER_FILE,
brw_inst_3src_src1_reg_nr(brw, inst));
brw_inst_3src_src1_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (src1_subreg_nr)
format(file, ".%d", src1_subreg_nr);
if (brw_inst_3src_src1_rep_ctrl(brw, inst))
if (brw_inst_3src_src1_rep_ctrl(devinfo, inst))
string(file, "<0,1,0>");
else
string(file, "<4,4,1>");
err |= src_swizzle(file, brw_inst_3src_src1_swizzle(brw, inst));
err |= src_swizzle(file, brw_inst_3src_src1_swizzle(devinfo, inst));
err |= control(file, "src da16 reg type", three_source_reg_encoding,
brw_inst_3src_src_type(brw, inst), NULL);
brw_inst_3src_src_type(devinfo, inst), NULL);
return err;
}
@ -992,59 +996,61 @@ static int
src2_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
{
int err = 0;
unsigned src2_subreg_nr = brw_inst_3src_src2_subreg_nr(brw, inst);
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
unsigned src2_subreg_nr = brw_inst_3src_src2_subreg_nr(devinfo, inst);
err |= control(file, "negate", m_negate,
brw_inst_3src_src2_negate(brw, inst), NULL);
err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(brw, inst), NULL);
brw_inst_3src_src2_negate(devinfo, inst), NULL);
err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(devinfo, inst), NULL);
err |= reg(file, BRW_GENERAL_REGISTER_FILE,
brw_inst_3src_src2_reg_nr(brw, inst));
brw_inst_3src_src2_reg_nr(devinfo, inst));
if (err == -1)
return 0;
if (src2_subreg_nr)
format(file, ".%d", src2_subreg_nr);
if (brw_inst_3src_src2_rep_ctrl(brw, inst))
if (brw_inst_3src_src2_rep_ctrl(devinfo, inst))
string(file, "<0,1,0>");
else
string(file, "<4,4,1>");
err |= src_swizzle(file, brw_inst_3src_src2_swizzle(brw, inst));
err |= src_swizzle(file, brw_inst_3src_src2_swizzle(devinfo, inst));
err |= control(file, "src da16 reg type", three_source_reg_encoding,
brw_inst_3src_src_type(brw, inst), NULL);
brw_inst_3src_src_type(devinfo, inst), NULL);
return err;
}
static int
imm(FILE *file, struct brw_context *brw, unsigned type, brw_inst *inst)
{
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
switch (type) {
case BRW_HW_REG_TYPE_UD:
format(file, "0x%08xUD", brw_inst_imm_ud(brw, inst));
format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
break;
case BRW_HW_REG_TYPE_D:
format(file, "%dD", brw_inst_imm_d(brw, inst));
format(file, "%dD", brw_inst_imm_d(devinfo, inst));
break;
case BRW_HW_REG_TYPE_UW:
format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(brw, inst));
format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
break;
case BRW_HW_REG_TYPE_W:
format(file, "%dW", (int16_t) brw_inst_imm_d(brw, inst));
format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst));
break;
case BRW_HW_REG_IMM_TYPE_UV:
format(file, "0x%08xUV", brw_inst_imm_ud(brw, inst));
format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst));
break;
case BRW_HW_REG_IMM_TYPE_VF:
format(file, "[%-gF, %-gF, %-gF, %-gF]VF",
brw_vf_to_float(brw_inst_imm_ud(brw, inst)),
brw_vf_to_float(brw_inst_imm_ud(brw, inst) >> 8),
brw_vf_to_float(brw_inst_imm_ud(brw, inst) >> 16),
brw_vf_to_float(brw_inst_imm_ud(brw, inst) >> 24));
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
break;
case BRW_HW_REG_IMM_TYPE_V:
format(file, "0x%08xV", brw_inst_imm_ud(brw, inst));
format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
break;
case BRW_HW_REG_TYPE_F:
format(file, "%-gF", brw_inst_imm_f(brw, inst));
format(file, "%-gF", brw_inst_imm_f(devinfo, inst));
break;
case GEN8_HW_REG_IMM_TYPE_DF:
string(file, "Double IMM");
@ -1059,53 +1065,54 @@ imm(FILE *file, struct brw_context *brw, unsigned type, brw_inst *inst)
static int
src0(FILE *file, struct brw_context *brw, brw_inst *inst)
{
if (brw_inst_src0_reg_file(brw, inst) == BRW_IMMEDIATE_VALUE) {
return imm(file, brw, brw_inst_src0_reg_type(brw, inst), inst);
} else if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
if (brw_inst_src0_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
return imm(file, brw, brw_inst_src0_reg_type(devinfo, inst), inst);
} else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
return src_da1(file,
brw,
brw_inst_opcode(brw, inst),
brw_inst_src0_reg_type(brw, inst),
brw_inst_src0_reg_file(brw, inst),
brw_inst_src0_vstride(brw, inst),
brw_inst_src0_width(brw, inst),
brw_inst_src0_hstride(brw, inst),
brw_inst_src0_da_reg_nr(brw, inst),
brw_inst_src0_da1_subreg_nr(brw, inst),
brw_inst_src0_abs(brw, inst),
brw_inst_src0_negate(brw, inst));
brw_inst_opcode(devinfo, inst),
brw_inst_src0_reg_type(devinfo, inst),
brw_inst_src0_reg_file(devinfo, inst),
brw_inst_src0_vstride(devinfo, inst),
brw_inst_src0_width(devinfo, inst),
brw_inst_src0_hstride(devinfo, inst),
brw_inst_src0_da_reg_nr(devinfo, inst),
brw_inst_src0_da1_subreg_nr(devinfo, inst),
brw_inst_src0_abs(devinfo, inst),
brw_inst_src0_negate(devinfo, inst));
} else {
return src_ia1(file,
brw,
brw_inst_opcode(brw, inst),
brw_inst_src0_reg_type(brw, inst),
brw_inst_src0_reg_file(brw, inst),
brw_inst_src0_ia1_addr_imm(brw, inst),
brw_inst_src0_ia_subreg_nr(brw, inst),
brw_inst_src0_negate(brw, inst),
brw_inst_src0_abs(brw, inst),
brw_inst_src0_address_mode(brw, inst),
brw_inst_src0_hstride(brw, inst),
brw_inst_src0_width(brw, inst),
brw_inst_src0_vstride(brw, inst));
brw_inst_opcode(devinfo, inst),
brw_inst_src0_reg_type(devinfo, inst),
brw_inst_src0_reg_file(devinfo, inst),
brw_inst_src0_ia1_addr_imm(devinfo, inst),
brw_inst_src0_ia_subreg_nr(devinfo, inst),
brw_inst_src0_negate(devinfo, inst),
brw_inst_src0_abs(devinfo, inst),
brw_inst_src0_address_mode(devinfo, inst),
brw_inst_src0_hstride(devinfo, inst),
brw_inst_src0_width(devinfo, inst),
brw_inst_src0_vstride(devinfo, inst));
}
} else {
if (brw_inst_src0_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
return src_da16(file,
brw,
brw_inst_opcode(brw, inst),
brw_inst_src0_reg_type(brw, inst),
brw_inst_src0_reg_file(brw, inst),
brw_inst_src0_vstride(brw, inst),
brw_inst_src0_da_reg_nr(brw, inst),
brw_inst_src0_da16_subreg_nr(brw, inst),
brw_inst_src0_abs(brw, inst),
brw_inst_src0_negate(brw, inst),
brw_inst_src0_da16_swiz_x(brw, inst),
brw_inst_src0_da16_swiz_y(brw, inst),
brw_inst_src0_da16_swiz_z(brw, inst),
brw_inst_src0_da16_swiz_w(brw, inst));
brw_inst_opcode(devinfo, inst),
brw_inst_src0_reg_type(devinfo, inst),
brw_inst_src0_reg_file(devinfo, inst),
brw_inst_src0_vstride(devinfo, inst),
brw_inst_src0_da_reg_nr(devinfo, inst),
brw_inst_src0_da16_subreg_nr(devinfo, inst),
brw_inst_src0_abs(devinfo, inst),
brw_inst_src0_negate(devinfo, inst),
brw_inst_src0_da16_swiz_x(devinfo, inst),
brw_inst_src0_da16_swiz_y(devinfo, inst),
brw_inst_src0_da16_swiz_z(devinfo, inst),
brw_inst_src0_da16_swiz_w(devinfo, inst));
} else {
string(file, "Indirect align16 address mode not supported");
return 1;
@ -1116,53 +1123,54 @@ src0(FILE *file, struct brw_context *brw, brw_inst *inst)
static int
src1(FILE *file, struct brw_context *brw, brw_inst *inst)
{
if (brw_inst_src1_reg_file(brw, inst) == BRW_IMMEDIATE_VALUE) {
return imm(file, brw, brw_inst_src1_reg_type(brw, inst), inst);
} else if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
if (brw_inst_src1_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
return imm(file, brw, brw_inst_src1_reg_type(devinfo, inst), inst);
} else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
return src_da1(file,
brw,
brw_inst_opcode(brw, inst),
brw_inst_src1_reg_type(brw, inst),
brw_inst_src1_reg_file(brw, inst),
brw_inst_src1_vstride(brw, inst),
brw_inst_src1_width(brw, inst),
brw_inst_src1_hstride(brw, inst),
brw_inst_src1_da_reg_nr(brw, inst),
brw_inst_src1_da1_subreg_nr(brw, inst),
brw_inst_src1_abs(brw, inst),
brw_inst_src1_negate(brw, inst));
brw_inst_opcode(devinfo, inst),
brw_inst_src1_reg_type(devinfo, inst),
brw_inst_src1_reg_file(devinfo, inst),
brw_inst_src1_vstride(devinfo, inst),
brw_inst_src1_width(devinfo, inst),
brw_inst_src1_hstride(devinfo, inst),
brw_inst_src1_da_reg_nr(devinfo, inst),
brw_inst_src1_da1_subreg_nr(devinfo, inst),
brw_inst_src1_abs(devinfo, inst),
brw_inst_src1_negate(devinfo, inst));
} else {
return src_ia1(file,
brw,
brw_inst_opcode(brw, inst),
brw_inst_src1_reg_type(brw, inst),
brw_inst_src1_reg_file(brw, inst),
brw_inst_src1_ia1_addr_imm(brw, inst),
brw_inst_src1_ia_subreg_nr(brw, inst),
brw_inst_src1_negate(brw, inst),
brw_inst_src1_abs(brw, inst),
brw_inst_src1_address_mode(brw, inst),
brw_inst_src1_hstride(brw, inst),
brw_inst_src1_width(brw, inst),
brw_inst_src1_vstride(brw, inst));
brw_inst_opcode(devinfo, inst),
brw_inst_src1_reg_type(devinfo, inst),
brw_inst_src1_reg_file(devinfo, inst),
brw_inst_src1_ia1_addr_imm(devinfo, inst),
brw_inst_src1_ia_subreg_nr(devinfo, inst),
brw_inst_src1_negate(devinfo, inst),
brw_inst_src1_abs(devinfo, inst),
brw_inst_src1_address_mode(devinfo, inst),
brw_inst_src1_hstride(devinfo, inst),
brw_inst_src1_width(devinfo, inst),
brw_inst_src1_vstride(devinfo, inst));
}
} else {
if (brw_inst_src1_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
return src_da16(file,
brw,
brw_inst_opcode(brw, inst),
brw_inst_src1_reg_type(brw, inst),
brw_inst_src1_reg_file(brw, inst),
brw_inst_src1_vstride(brw, inst),
brw_inst_src1_da_reg_nr(brw, inst),
brw_inst_src1_da16_subreg_nr(brw, inst),
brw_inst_src1_abs(brw, inst),
brw_inst_src1_negate(brw, inst),
brw_inst_src1_da16_swiz_x(brw, inst),
brw_inst_src1_da16_swiz_y(brw, inst),
brw_inst_src1_da16_swiz_z(brw, inst),
brw_inst_src1_da16_swiz_w(brw, inst));
brw_inst_opcode(devinfo, inst),
brw_inst_src1_reg_type(devinfo, inst),
brw_inst_src1_reg_file(devinfo, inst),
brw_inst_src1_vstride(devinfo, inst),
brw_inst_src1_da_reg_nr(devinfo, inst),
brw_inst_src1_da16_subreg_nr(devinfo, inst),
brw_inst_src1_abs(devinfo, inst),
brw_inst_src1_negate(devinfo, inst),
brw_inst_src1_da16_swiz_x(devinfo, inst),
brw_inst_src1_da16_swiz_y(devinfo, inst),
brw_inst_src1_da16_swiz_z(devinfo, inst),
brw_inst_src1_da16_swiz_w(devinfo, inst));
} else {
string(file, "Indirect align16 address mode not supported");
return 1;
@ -1173,8 +1181,9 @@ src1(FILE *file, struct brw_context *brw, brw_inst *inst)
static int
qtr_ctrl(FILE *file, struct brw_context *brw, brw_inst *inst)
{
int qtr_ctl = brw_inst_qtr_control(brw, inst);
int exec_size = 1 << brw_inst_exec_size(brw, inst);
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
if (exec_size == 8) {
switch (qtr_ctl) {
@ -1218,94 +1227,95 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
{
int err = 0;
int space = 0;
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
const enum opcode opcode = brw_inst_opcode(brw, inst);
const enum opcode opcode = brw_inst_opcode(devinfo, inst);
if (brw_inst_pred_control(brw, inst)) {
if (brw_inst_pred_control(devinfo, inst)) {
string(file, "(");
err |= control(file, "predicate inverse", pred_inv,
brw_inst_pred_inv(brw, inst), NULL);
format(file, "f%ld", brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, inst) : 0);
if (brw_inst_flag_subreg_nr(brw, inst))
format(file, ".%ld", brw_inst_flag_subreg_nr(brw, inst));
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
brw_inst_pred_inv(devinfo, inst), NULL);
format(file, "f%ld", devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0);
if (brw_inst_flag_subreg_nr(devinfo, inst))
format(file, ".%ld", brw_inst_flag_subreg_nr(devinfo, inst));
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
err |= control(file, "predicate control align1", pred_ctrl_align1,
brw_inst_pred_control(brw, inst), NULL);
brw_inst_pred_control(devinfo, inst), NULL);
} else {
err |= control(file, "predicate control align16", pred_ctrl_align16,
brw_inst_pred_control(brw, inst), NULL);
brw_inst_pred_control(devinfo, inst), NULL);
}
string(file, ") ");
}
err |= print_opcode(file, opcode);
err |= control(file, "saturate", saturate, brw_inst_saturate(brw, inst),
err |= control(file, "saturate", saturate, brw_inst_saturate(devinfo, inst),
NULL);
err |= control(file, "debug control", debug_ctrl,
brw_inst_debug_control(brw, inst), NULL);
brw_inst_debug_control(devinfo, inst), NULL);
if (opcode == BRW_OPCODE_MATH) {
string(file, " ");
err |= control(file, "function", math_function,
brw_inst_math_function(brw, inst), NULL);
brw_inst_math_function(devinfo, inst), NULL);
} else if (opcode != BRW_OPCODE_SEND && opcode != BRW_OPCODE_SENDC) {
err |= control(file, "conditional modifier", conditional_modifier,
brw_inst_cond_modifier(brw, inst), NULL);
brw_inst_cond_modifier(devinfo, inst), NULL);
/* If we're using the conditional modifier, print which flags reg is
* used for it. Note that on gen6+, the embedded-condition SEL and
* control flow doesn't update flags.
*/
if (brw_inst_cond_modifier(brw, inst) &&
if (brw_inst_cond_modifier(devinfo, inst) &&
(brw->gen < 6 || (opcode != BRW_OPCODE_SEL &&
opcode != BRW_OPCODE_IF &&
opcode != BRW_OPCODE_WHILE))) {
format(file, ".f%ld",
brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, inst) : 0);
if (brw_inst_flag_subreg_nr(brw, inst))
format(file, ".%ld", brw_inst_flag_subreg_nr(brw, inst));
brw->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0);
if (brw_inst_flag_subreg_nr(devinfo, inst))
format(file, ".%ld", brw_inst_flag_subreg_nr(devinfo, inst));
}
}
if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
string(file, "(");
err |= control(file, "execution size", exec_size,
brw_inst_exec_size(brw, inst), NULL);
brw_inst_exec_size(devinfo, inst), NULL);
string(file, ")");
}
if (opcode == BRW_OPCODE_SEND && brw->gen < 6)
format(file, " %ld", brw_inst_base_mrf(brw, inst));
format(file, " %ld", brw_inst_base_mrf(devinfo, inst));
if (has_uip(brw, opcode)) {
/* Instructions that have UIP also have JIP. */
pad(file, 16);
format(file, "JIP: %d", brw_inst_jip(brw, inst));
format(file, "JIP: %d", brw_inst_jip(devinfo, inst));
pad(file, 32);
format(file, "UIP: %d", brw_inst_uip(brw, inst));
format(file, "UIP: %d", brw_inst_uip(devinfo, inst));
} else if (has_jip(brw, opcode)) {
pad(file, 16);
if (brw->gen >= 7) {
format(file, "JIP: %d", brw_inst_jip(brw, inst));
format(file, "JIP: %d", brw_inst_jip(devinfo, inst));
} else {
format(file, "JIP: %d", brw_inst_gen6_jump_count(brw, inst));
format(file, "JIP: %d", brw_inst_gen6_jump_count(devinfo, inst));
}
} else if (brw->gen < 6 && (opcode == BRW_OPCODE_BREAK ||
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_ELSE)) {
pad(file, 16);
format(file, "Jump: %d", brw_inst_gen4_jump_count(brw, inst));
format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
pad(file, 32);
format(file, "Pop: %ld", brw_inst_gen4_pop_count(brw, inst));
format(file, "Pop: %ld", brw_inst_gen4_pop_count(devinfo, inst));
} else if (brw->gen < 6 && (opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_IFF ||
opcode == BRW_OPCODE_HALT)) {
pad(file, 16);
format(file, "Jump: %d", brw_inst_gen4_jump_count(brw, inst));
format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
} else if (brw->gen < 6 && opcode == BRW_OPCODE_ENDIF) {
pad(file, 16);
format(file, "Pop: %ld", brw_inst_gen4_pop_count(brw, inst));
format(file, "Pop: %ld", brw_inst_gen4_pop_count(devinfo, inst));
} else if (opcode == BRW_OPCODE_JMPI) {
pad(file, 16);
err |= src1(file, brw, inst);
@ -1339,9 +1349,9 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
}
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
enum brw_message_target sfid = brw_inst_sfid(brw, inst);
enum brw_message_target sfid = brw_inst_sfid(devinfo, inst);
if (brw_inst_src1_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE) {
if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
/* show the indirect descriptor source */
pad(file, 48);
err |= src1(file, brw, inst);
@ -1356,38 +1366,38 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
sfid, &space);
if (brw_inst_src1_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE) {
if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
format(file, " indirect");
} else {
switch (sfid) {
case BRW_SFID_MATH:
err |= control(file, "math function", math_function,
brw_inst_math_msg_function(brw, inst), &space);
brw_inst_math_msg_function(devinfo, inst), &space);
err |= control(file, "math saturate", math_saturate,
brw_inst_math_msg_saturate(brw, inst), &space);
brw_inst_math_msg_saturate(devinfo, inst), &space);
err |= control(file, "math signed", math_signed,
brw_inst_math_msg_signed_int(brw, inst), &space);
brw_inst_math_msg_signed_int(devinfo, inst), &space);
err |= control(file, "math scalar", math_scalar,
brw_inst_math_msg_data_type(brw, inst), &space);
brw_inst_math_msg_data_type(devinfo, inst), &space);
err |= control(file, "math precision", math_precision,
brw_inst_math_msg_precision(brw, inst), &space);
brw_inst_math_msg_precision(devinfo, inst), &space);
break;
case BRW_SFID_SAMPLER:
if (brw->gen >= 5) {
format(file, " (%ld, %ld, %ld, %ld)",
brw_inst_binding_table_index(brw, inst),
brw_inst_sampler(brw, inst),
brw_inst_sampler_msg_type(brw, inst),
brw_inst_sampler_simd_mode(brw, inst));
brw_inst_binding_table_index(devinfo, inst),
brw_inst_sampler(devinfo, inst),
brw_inst_sampler_msg_type(devinfo, inst),
brw_inst_sampler_simd_mode(devinfo, inst));
} else {
format(file, " (%ld, %ld, %ld, ",
brw_inst_binding_table_index(brw, inst),
brw_inst_sampler(brw, inst),
brw_inst_sampler_msg_type(brw, inst));
brw_inst_binding_table_index(devinfo, inst),
brw_inst_sampler(devinfo, inst),
brw_inst_sampler_msg_type(devinfo, inst));
if (!brw->is_g4x) {
err |= control(file, "sampler target format",
sampler_target_format,
brw_inst_sampler_return_format(brw, inst), NULL);
brw_inst_sampler_return_format(devinfo, inst), NULL);
}
string(file, ")");
}
@ -1396,21 +1406,21 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
/* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
if (brw->gen >= 6) {
format(file, " (%ld, %ld, %ld, %ld)",
brw_inst_binding_table_index(brw, inst),
brw_inst_dp_msg_control(brw, inst),
brw_inst_dp_msg_type(brw, inst),
brw->gen >= 7 ? 0 : brw_inst_dp_write_commit(brw, inst));
brw_inst_binding_table_index(devinfo, inst),
brw_inst_dp_msg_control(devinfo, inst),
brw_inst_dp_msg_type(devinfo, inst),
brw->gen >= 7 ? 0 : brw_inst_dp_write_commit(devinfo, inst));
} else {
format(file, " (%ld, %ld, %ld)",
brw_inst_binding_table_index(brw, inst),
brw_inst_dp_read_msg_control(brw, inst),
brw_inst_dp_read_msg_type(brw, inst));
brw_inst_binding_table_index(devinfo, inst),
brw_inst_dp_read_msg_control(devinfo, inst),
brw_inst_dp_read_msg_type(devinfo, inst));
}
break;
case GEN6_SFID_DATAPORT_RENDER_CACHE: {
/* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
unsigned msg_type = brw_inst_dp_write_msg_type(brw, inst);
unsigned msg_type = brw_inst_dp_write_msg_type(devinfo, inst);
err |= control(file, "DP rc message type",
brw->gen >= 6 ? dp_rc_msg_type_gen6
@ -1423,44 +1433,44 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
if (is_rt_write) {
err |= control(file, "RT message type", m_rt_write_subtype,
brw_inst_rt_message_type(brw, inst), &space);
if (brw->gen >= 6 && brw_inst_rt_slot_group(brw, inst))
brw_inst_rt_message_type(devinfo, inst), &space);
if (brw->gen >= 6 && brw_inst_rt_slot_group(devinfo, inst))
string(file, " Hi");
if (brw_inst_rt_last(brw, inst))
if (brw_inst_rt_last(devinfo, inst))
string(file, " LastRT");
if (brw->gen < 7 && brw_inst_dp_write_commit(brw, inst))
if (brw->gen < 7 && brw_inst_dp_write_commit(devinfo, inst))
string(file, " WriteCommit");
} else {
format(file, " MsgCtrl = 0x%lx",
brw_inst_dp_write_msg_control(brw, inst));
brw_inst_dp_write_msg_control(devinfo, inst));
}
format(file, " Surface = %ld", brw_inst_binding_table_index(brw, inst));
format(file, " Surface = %ld", brw_inst_binding_table_index(devinfo, inst));
break;
}
case BRW_SFID_URB:
format(file, " %ld", brw_inst_urb_global_offset(brw, inst));
format(file, " %ld", brw_inst_urb_global_offset(devinfo, inst));
space = 1;
if (brw->gen >= 7) {
err |= control(file, "urb opcode", gen7_urb_opcode,
brw_inst_urb_opcode(brw, inst), &space);
brw_inst_urb_opcode(devinfo, inst), &space);
} else if (brw->gen >= 5) {
err |= control(file, "urb opcode", gen5_urb_opcode,
brw_inst_urb_opcode(brw, inst), &space);
brw_inst_urb_opcode(devinfo, inst), &space);
}
err |= control(file, "urb swizzle", urb_swizzle,
brw_inst_urb_swizzle_control(brw, inst), &space);
brw_inst_urb_swizzle_control(devinfo, inst), &space);
if (brw->gen < 7) {
err |= control(file, "urb allocate", urb_allocate,
brw_inst_urb_allocate(brw, inst), &space);
brw_inst_urb_allocate(devinfo, inst), &space);
err |= control(file, "urb used", urb_used,
brw_inst_urb_used(brw, inst), &space);
brw_inst_urb_used(devinfo, inst), &space);
}
if (brw->gen < 8) {
err |= control(file, "urb complete", urb_complete,
brw_inst_urb_complete(brw, inst), &space);
brw_inst_urb_complete(devinfo, inst), &space);
}
break;
case BRW_SFID_THREAD_SPAWNER:
@ -1471,17 +1481,17 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
err |= control(file, "DP DC0 message type",
dp_dc0_msg_type_gen7,
brw_inst_dp_msg_type(brw, inst), &space);
brw_inst_dp_msg_type(devinfo, inst), &space);
format(file, ", %ld, ", brw_inst_binding_table_index(brw, inst));
format(file, ", %ld, ", brw_inst_binding_table_index(devinfo, inst));
switch (brw_inst_dp_msg_type(brw, inst)) {
switch (brw_inst_dp_msg_type(devinfo, inst)) {
case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
control(file, "atomic op", aop,
brw_inst_imm_ud(brw, inst) >> 8 & 0xf, &space);
brw_inst_imm_ud(devinfo, inst) >> 8 & 0xf, &space);
break;
default:
format(file, "%ld", brw_inst_dp_msg_control(brw, inst));
format(file, "%ld", brw_inst_dp_msg_control(devinfo, inst));
}
format(file, ")");
break;
@ -1492,16 +1502,16 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
if (brw->gen >= 7) {
format(file, " (");
unsigned msg_ctrl = brw_inst_dp_msg_control(brw, inst);
unsigned msg_ctrl = brw_inst_dp_msg_control(devinfo, inst);
err |= control(file, "DP DC1 message type",
dp_dc1_msg_type_hsw,
brw_inst_dp_msg_type(brw, inst), &space);
brw_inst_dp_msg_type(devinfo, inst), &space);
format(file, ", Surface = %ld, ",
brw_inst_binding_table_index(brw, inst));
brw_inst_binding_table_index(devinfo, inst));
switch (brw_inst_dp_msg_type(brw, inst)) {
switch (brw_inst_dp_msg_type(devinfo, inst)) {
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
@ -1533,9 +1543,9 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
case GEN7_SFID_PIXEL_INTERPOLATOR:
if (brw->gen >= 7) {
format(file, " (%s, %s, 0x%02lx)",
brw_inst_pi_nopersp(brw, inst) ? "linear" : "persp",
pixel_interpolator_msg_types[brw_inst_pi_message_type(brw, inst)],
brw_inst_pi_message_data(brw, inst));
brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp",
pixel_interpolator_msg_types[brw_inst_pi_message_type(devinfo, inst)],
brw_inst_pi_message_data(devinfo, inst));
break;
}
/* FALLTHROUGH */
@ -1547,8 +1557,8 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
if (space)
string(file, " ");
format(file, "mlen %ld", brw_inst_mlen(brw, inst));
format(file, " rlen %ld", brw_inst_rlen(brw, inst));
format(file, "mlen %ld", brw_inst_mlen(devinfo, inst));
format(file, " rlen %ld", brw_inst_rlen(devinfo, inst));
}
}
pad(file, 64);
@ -1556,45 +1566,45 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
string(file, "{");
space = 1;
err |= control(file, "access mode", access_mode,
brw_inst_access_mode(brw, inst), &space);
brw_inst_access_mode(devinfo, inst), &space);
if (brw->gen >= 6) {
err |= control(file, "write enable control", wectrl,
brw_inst_mask_control(brw, inst), &space);
brw_inst_mask_control(devinfo, inst), &space);
} else {
err |= control(file, "mask control", mask_ctrl,
brw_inst_mask_control(brw, inst), &space);
brw_inst_mask_control(devinfo, inst), &space);
}
err |= control(file, "dependency control", dep_ctrl,
((brw_inst_no_dd_check(brw, inst) << 1) |
brw_inst_no_dd_clear(brw, inst)), &space);
((brw_inst_no_dd_check(devinfo, inst) << 1) |
brw_inst_no_dd_clear(devinfo, inst)), &space);
if (brw->gen >= 6)
err |= qtr_ctrl(file, brw, inst);
else {
if (brw_inst_qtr_control(brw, inst) == BRW_COMPRESSION_COMPRESSED &&
if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED &&
opcode_descs[opcode].ndst > 0 &&
brw_inst_dst_reg_file(brw, inst) == BRW_MESSAGE_REGISTER_FILE &&
brw_inst_dst_da_reg_nr(brw, inst) & (1 << 7)) {
brw_inst_dst_reg_file(devinfo, inst) == BRW_MESSAGE_REGISTER_FILE &&
brw_inst_dst_da_reg_nr(devinfo, inst) & (1 << 7)) {
format(file, " compr4");
} else {
err |= control(file, "compression control", compr_ctrl,
brw_inst_qtr_control(brw, inst), &space);
brw_inst_qtr_control(devinfo, inst), &space);
}
}
err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
err |= control(file, "thread control", thread_ctrl,
brw_inst_thread_control(brw, inst), &space);
brw_inst_thread_control(devinfo, inst), &space);
if (has_branch_ctrl(brw, opcode)) {
err |= control(file, "branch ctrl", branch_ctrl,
brw_inst_branch_control(brw, inst), &space);
brw_inst_branch_control(devinfo, inst), &space);
} else if (brw->gen >= 6) {
err |= control(file, "acc write control", accwr,
brw_inst_acc_wr_control(brw, inst), &space);
brw_inst_acc_wr_control(devinfo, inst), &space);
}
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC)
err |= control(file, "end of thread", end_of_thread,
brw_inst_eot(brw, inst), &space);
brw_inst_eot(devinfo, inst), &space);
if (space)
string(file, " ");
string(file, "}");

28
src/mesa/drivers/dri/i965/brw_eu.c
View file

@ -113,30 +113,30 @@ brw_swap_cmod(uint32_t cmod)
void
brw_set_default_exec_size(struct brw_compile *p, unsigned value)
{
brw_inst_set_exec_size(p->brw, p->current, value);
brw_inst_set_exec_size(p->devinfo, p->current, value);
}
void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc )
{
brw_inst_set_pred_control(p->brw, p->current, pc);
brw_inst_set_pred_control(p->devinfo, p->current, pc);
}
void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
{
brw_inst_set_pred_inv(p->brw, p->current, predicate_inverse);
brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
}
void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg)
{
if (p->brw->gen >= 7)
brw_inst_set_flag_reg_nr(p->brw, p->current, reg);
brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
brw_inst_set_flag_subreg_nr(p->brw, p->current, subreg);
brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
}
void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode )
{
brw_inst_set_access_mode(p->brw, p->current, access_mode);
brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
}
void
@ -156,34 +156,34 @@ brw_set_default_compression_control(struct brw_compile *p,
/* This is the "use the first set of bits of dmask/vmask/arf
* according to execsize" option.
*/
brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1Q);
brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
break;
case BRW_COMPRESSION_2NDHALF:
/* For SIMD8, this is "use the second set of 8 bits." */
brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_2Q);
brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
break;
case BRW_COMPRESSION_COMPRESSED:
/* For SIMD16 instruction compression, use the first set of 16 bits
* since we don't do SIMD32 dispatch.
*/
brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
break;
default:
unreachable("not reached");
}
} else {
brw_inst_set_qtr_control(brw, p->current, compression_control);
brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
}
}
void brw_set_default_mask_control( struct brw_compile *p, unsigned value )
{
brw_inst_set_mask_control(p->brw, p->current, value);
brw_inst_set_mask_control(p->devinfo, p->current, value);
}
void brw_set_default_saturate( struct brw_compile *p, bool enable )
{
brw_inst_set_saturate(p->brw, p->current, enable);
brw_inst_set_saturate(p->devinfo, p->current, enable);
}
void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
@ -191,7 +191,7 @@ void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
struct brw_context *brw = p->brw;
if (brw->gen >= 6)
brw_inst_set_acc_wr_control(p->brw, p->current, value);
brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
}
void brw_push_insn_state( struct brw_compile *p )
@ -270,7 +270,7 @@ brw_disassemble(struct brw_context *brw,
for (int offset = start; offset < end;) {
brw_inst *insn = assembly + offset;
brw_inst uncompacted;
bool compacted = brw_inst_cmpt_control(brw, insn);
bool compacted = brw_inst_cmpt_control(brw->intelScreen->devinfo, insn);
if (0)
fprintf(out, "0x%08x: ", offset);

10
src/mesa/drivers/dri/i965/brw_eu.h
View file

@ -346,16 +346,16 @@ void brw_shader_time_add(struct brw_compile *p,
* instruction.
*/
static inline unsigned
brw_jump_scale(const struct brw_context *brw)
brw_jump_scale(const struct brw_device_info *devinfo)
{
/* Broadwell measures jump targets in bytes. */
if (brw->gen >= 8)
if (devinfo->gen >= 8)
return 16;
/* Ironlake and later measure jump targets in 64-bit data chunks (in order
* (to support compaction), so each 128-bit instruction requires 2 chunks.
*/
if (brw->gen >= 5)
if (devinfo->gen >= 5)
return 2;
/* Gen4 simply uses the number of 128-bit instructions. */
@ -475,11 +475,11 @@ void brw_debug_compact_uncompact(struct brw_context *brw, brw_inst *orig,
brw_inst *uncompacted);
static inline int
next_offset(const struct brw_context *brw, void *store, int offset)
next_offset(const struct brw_device_info *devinfo, void *store, int offset)
{
brw_inst *insn = (brw_inst *)((char *)store + offset);
if (brw_inst_cmpt_control(brw, insn))
if (brw_inst_cmpt_control(devinfo, insn))
return offset + 8;
else
return offset + 16;

123
src/mesa/drivers/dri/i965/brw_eu_compact.c
View file

@ -774,7 +774,7 @@ set_src1_index(struct brw_context *brw, brw_compact_inst *dst, brw_inst *src,
uint16_t compacted;
if (is_immediate) {
compacted = (brw_inst_imm_ud(brw, src) >> 8) & 0x1f;
compacted = (brw_inst_imm_ud(brw->intelScreen->devinfo, src) >> 8) & 0x1f;
} else {
uint16_t uncompacted = brw_inst_bits(src, 120, 109); /* 12b */
@ -898,8 +898,9 @@ brw_try_compact_3src_instruction(struct brw_context *brw, brw_compact_inst *dst,
if (has_3src_unmapped_bits(brw, src))
return false;
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
#define compact(field) \
brw_compact_inst_set_3src_##field(dst, brw_inst_3src_##field(brw, src))
brw_compact_inst_set_3src_##field(dst, brw_inst_3src_##field(devinfo, src))
compact(opcode);
@ -961,11 +962,12 @@ bool
brw_try_compact_instruction(struct brw_context *brw, brw_compact_inst *dst,
brw_inst *src)
{
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
brw_compact_inst temp;
assert(brw_inst_cmpt_control(brw, src) == 0);
assert(brw_inst_cmpt_control(devinfo, src) == 0);
if (is_3src(brw_inst_opcode(brw, src))) {
if (is_3src(brw_inst_opcode(devinfo, src))) {
if (brw->gen >= 8) {
memset(&temp, 0, sizeof(temp));
if (brw_try_compact_3src_instruction(brw, &temp, src)) {
@ -980,10 +982,10 @@ brw_try_compact_instruction(struct brw_context *brw, brw_compact_inst *dst,
}
bool is_immediate =
brw_inst_src0_reg_file(brw, src) == BRW_IMMEDIATE_VALUE ||
brw_inst_src1_reg_file(brw, src) == BRW_IMMEDIATE_VALUE;
brw_inst_src0_reg_file(devinfo, src) == BRW_IMMEDIATE_VALUE ||
brw_inst_src1_reg_file(devinfo, src) == BRW_IMMEDIATE_VALUE;
if (is_immediate &&
(brw->gen < 6 || !is_compactable_immediate(brw_inst_imm_ud(brw, src)))) {
(brw->gen < 6 || !is_compactable_immediate(brw_inst_imm_ud(devinfo, src)))) {
return false;
}
@ -992,8 +994,8 @@ brw_try_compact_instruction(struct brw_context *brw, brw_compact_inst *dst,
memset(&temp, 0, sizeof(temp));
brw_compact_inst_set_opcode(&temp, brw_inst_opcode(brw, src));
brw_compact_inst_set_debug_control(&temp, brw_inst_debug_control(brw, src));
brw_compact_inst_set_opcode(&temp, brw_inst_opcode(devinfo, src));
brw_compact_inst_set_debug_control(&temp, brw_inst_debug_control(devinfo, src));
if (!set_control_index(brw, &temp, src))
return false;
if (!set_datatype_index(brw, &temp, src))
@ -1001,23 +1003,25 @@ brw_try_compact_instruction(struct brw_context *brw, brw_compact_inst *dst,
if (!set_subreg_index(brw, &temp, src, is_immediate))
return false;
brw_compact_inst_set_acc_wr_control(&temp,
brw_inst_acc_wr_control(brw, src));
brw_compact_inst_set_cond_modifier(&temp, brw_inst_cond_modifier(brw, src));
brw_inst_acc_wr_control(devinfo, src));
brw_compact_inst_set_cond_modifier(&temp,
brw_inst_cond_modifier(devinfo, src));
if (brw->gen <= 6)
brw_compact_inst_set_flag_subreg_nr(&temp,
brw_inst_flag_subreg_nr(brw, src));
brw_inst_flag_subreg_nr(devinfo, src));
brw_compact_inst_set_cmpt_control(&temp, true);
if (!set_src0_index(brw, &temp, src))
return false;
if (!set_src1_index(brw, &temp, src, is_immediate))
return false;
brw_compact_inst_set_dst_reg_nr(&temp, brw_inst_dst_da_reg_nr(brw, src));
brw_compact_inst_set_src0_reg_nr(&temp, brw_inst_src0_da_reg_nr(brw, src));
brw_compact_inst_set_dst_reg_nr(&temp, brw_inst_dst_da_reg_nr(devinfo, src));
brw_compact_inst_set_src0_reg_nr(&temp, brw_inst_src0_da_reg_nr(devinfo, src));
if (is_immediate) {
brw_compact_inst_set_src1_reg_nr(&temp, brw_inst_imm_ud(brw, src) & 0xff);
brw_compact_inst_set_src1_reg_nr(&temp,
brw_inst_imm_ud(devinfo, src) & 0xff);
} else {
brw_compact_inst_set_src1_reg_nr(&temp,
brw_inst_src1_da_reg_nr(brw, src));
brw_inst_src1_da_reg_nr(devinfo, src));
}
*dst = temp;
@ -1091,7 +1095,7 @@ set_uncompacted_src1(struct brw_context *brw, brw_inst *dst,
if (is_immediate) {
signed high5 = brw_compact_inst_src1_index(src);
/* Replicate top bit of src1_index into high 20 bits of the immediate. */
brw_inst_set_imm_ud(brw, dst, (high5 << 27) >> 19);
brw_inst_set_imm_ud(brw->intelScreen->devinfo, dst, (high5 << 27) >> 19);
} else {
uint16_t uncompacted = src_index_table[brw_compact_inst_src1_index(src)];
@ -1146,8 +1150,9 @@ brw_uncompact_3src_instruction(struct brw_context *brw, brw_inst *dst,
{
assert(brw->gen >= 8);
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
#define uncompact(field) \
brw_inst_set_3src_##field(brw, dst, brw_compact_inst_3src_##field(src))
brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(src))
uncompact(opcode);
@ -1156,7 +1161,7 @@ brw_uncompact_3src_instruction(struct brw_context *brw, brw_inst *dst,
uncompact(dst_reg_nr);
uncompact(src0_rep_ctrl);
brw_inst_set_3src_cmpt_control(brw, dst, false);
brw_inst_set_3src_cmpt_control(devinfo, dst, false);
uncompact(debug_control);
uncompact(saturate);
uncompact(src1_rep_ctrl);
@ -1177,37 +1182,38 @@ brw_uncompact_instruction(struct brw_context *brw, brw_inst *dst,
{
memset(dst, 0, sizeof(*dst));
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
if (brw->gen >= 8 && is_3src(brw_compact_inst_3src_opcode(src))) {
brw_uncompact_3src_instruction(brw, dst, src);
return;
}
brw_inst_set_opcode(brw, dst, brw_compact_inst_opcode(src));
brw_inst_set_debug_control(brw, dst, brw_compact_inst_debug_control(src));
brw_inst_set_opcode(devinfo, dst, brw_compact_inst_opcode(src));
brw_inst_set_debug_control(devinfo, dst, brw_compact_inst_debug_control(src));
set_uncompacted_control(brw, dst, src);
set_uncompacted_datatype(brw, dst, src);
/* src0/1 register file fields are in the datatype table. */
bool is_immediate = brw_inst_src0_reg_file(brw, dst) == BRW_IMMEDIATE_VALUE ||
brw_inst_src1_reg_file(brw, dst) == BRW_IMMEDIATE_VALUE;
bool is_immediate = brw_inst_src0_reg_file(devinfo, dst) == BRW_IMMEDIATE_VALUE ||
brw_inst_src1_reg_file(devinfo, dst) == BRW_IMMEDIATE_VALUE;
set_uncompacted_subreg(brw, dst, src);
brw_inst_set_acc_wr_control(brw, dst, brw_compact_inst_acc_wr_control(src));
brw_inst_set_cond_modifier(brw, dst, brw_compact_inst_cond_modifier(src));
brw_inst_set_acc_wr_control(devinfo, dst, brw_compact_inst_acc_wr_control(src));
brw_inst_set_cond_modifier(devinfo, dst, brw_compact_inst_cond_modifier(src));
if (brw->gen <= 6)
brw_inst_set_flag_subreg_nr(brw, dst,
brw_inst_set_flag_subreg_nr(devinfo, dst,
brw_compact_inst_flag_subreg_nr(src));
set_uncompacted_src0(brw, dst, src);
set_uncompacted_src1(brw, dst, src, is_immediate);
brw_inst_set_dst_da_reg_nr(brw, dst, brw_compact_inst_dst_reg_nr(src));
brw_inst_set_src0_da_reg_nr(brw, dst, brw_compact_inst_src0_reg_nr(src));
brw_inst_set_dst_da_reg_nr(devinfo, dst, brw_compact_inst_dst_reg_nr(src));
brw_inst_set_src0_da_reg_nr(devinfo, dst, brw_compact_inst_src0_reg_nr(src));
if (is_immediate) {
brw_inst_set_imm_ud(brw, dst,
brw_inst_imm_ud(brw, dst) |
brw_inst_set_imm_ud(devinfo, dst,
brw_inst_imm_ud(devinfo, dst) |
brw_compact_inst_src1_reg_nr(src));
} else {
brw_inst_set_src1_da_reg_nr(brw, dst, brw_compact_inst_src1_reg_nr(src));
brw_inst_set_src1_da_reg_nr(devinfo, dst, brw_compact_inst_src1_reg_nr(src));
}
}
@ -1251,28 +1257,29 @@ static void
update_uip_jip(struct brw_context *brw, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
/* JIP and UIP are in units of:
* - bytes on Gen8+; and
* - compacted instructions on Gen6+.
*/
int shift = brw->gen >= 8 ? 3 : 0;
int32_t jip_compacted = brw_inst_jip(brw, insn) >> shift;
int32_t jip_compacted = brw_inst_jip(devinfo, insn) >> shift;
jip_compacted -= compacted_between(this_old_ip,
this_old_ip + (jip_compacted / 2),
compacted_counts);
brw_inst_set_jip(brw, insn, jip_compacted << shift);
brw_inst_set_jip(devinfo, insn, jip_compacted << shift);
if (brw_inst_opcode(brw, insn) == BRW_OPCODE_ENDIF ||
brw_inst_opcode(brw, insn) == BRW_OPCODE_WHILE ||
(brw_inst_opcode(brw, insn) == BRW_OPCODE_ELSE && brw->gen <= 7))
if (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ENDIF ||
brw_inst_opcode(devinfo, insn) == BRW_OPCODE_WHILE ||
(brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ELSE && brw->gen <= 7))
return;
int32_t uip_compacted = brw_inst_uip(brw, insn) >> shift;
int32_t uip_compacted = brw_inst_uip(devinfo, insn) >> shift;
uip_compacted -= compacted_between(this_old_ip,
this_old_ip + (uip_compacted / 2),
compacted_counts);
brw_inst_set_uip(brw, insn, uip_compacted << shift);
brw_inst_set_uip(devinfo, insn, uip_compacted << shift);
}
static void
@ -1281,13 +1288,14 @@ update_gen4_jump_count(struct brw_context *brw, brw_inst *insn,
{
assert(brw->gen == 5 || brw->is_g4x);
const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
/* Jump Count is in units of:
* - uncompacted instructions on G45; and
* - compacted instructions on Gen5.
*/
int shift = brw->is_g4x ? 1 : 0;
int jump_count_compacted = brw_inst_gen4_jump_count(brw, insn) << shift;
int jump_count_compacted = brw_inst_gen4_jump_count(devinfo, insn) << shift;
int target_old_ip = this_old_ip + (jump_count_compacted / 2);
@ -1295,7 +1303,7 @@ update_gen4_jump_count(struct brw_context *brw, brw_inst *insn,
int target_compacted_count = compacted_counts[target_old_ip];
jump_count_compacted -= (target_compacted_count - this_compacted_count);
brw_inst_set_gen4_jump_count(brw, insn, jump_count_compacted >> shift);
brw_inst_set_gen4_jump_count(devinfo, insn, jump_count_compacted >> shift);
}
void
@ -1359,6 +1367,7 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
int num_annotations, struct annotation *annotation)
{
struct brw_context *brw = p->brw;
const struct brw_device_info *devinfo = p->devinfo;
void *store = p->store + start_offset / 16;
/* For an instruction at byte offset 16*i before compaction, this is the
* number of compacted instructions minus the number of padding NOP/NENOPs
@ -1403,9 +1412,9 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
* aligned on G45.
*/
if ((offset & sizeof(brw_compact_inst)) != 0 &&
(((brw_inst_opcode(brw, src) == BRW_OPCODE_SEND ||
brw_inst_opcode(brw, src) == BRW_OPCODE_SENDC) &&
brw_inst_eot(brw, src)) ||
(((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SEND ||
brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC) &&
brw_inst_eot(devinfo, src)) ||
brw->is_g4x)) {
brw_compact_inst *align = store + offset;
memset(align, 0, sizeof(*align));
@ -1433,12 +1442,12 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
/* Fix up control flow offsets. */
p->next_insn_offset = start_offset + offset;
for (offset = 0; offset < p->next_insn_offset - start_offset;
offset = next_offset(brw, store, offset)) {
offset = next_offset(devinfo, store, offset)) {
brw_inst *insn = store + offset;
int this_old_ip = old_ip[offset / sizeof(brw_compact_inst)];
int this_compacted_count = compacted_counts[this_old_ip];
switch (brw_inst_opcode(brw, insn)) {
switch (brw_inst_opcode(devinfo, insn)) {
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_HALT:
@ -1455,7 +1464,7 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_WHILE:
if (brw->gen >= 7) {
if (brw_inst_cmpt_control(brw, insn)) {
if (brw_inst_cmpt_control(devinfo, insn)) {
brw_inst uncompacted;
brw_uncompact_instruction(brw, &uncompacted,
(brw_compact_inst *)insn);
@ -1470,15 +1479,15 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
update_uip_jip(brw, insn, this_old_ip, compacted_counts);
}
} else if (brw->gen == 6) {
assert(!brw_inst_cmpt_control(brw, insn));
assert(!brw_inst_cmpt_control(devinfo, insn));
/* Jump Count is in units of compacted instructions on Gen6. */
int jump_count_compacted = brw_inst_gen6_jump_count(brw, insn);
int jump_count_compacted = brw_inst_gen6_jump_count(devinfo, insn);
int target_old_ip = this_old_ip + (jump_count_compacted / 2);
int target_compacted_count = compacted_counts[target_old_ip];
jump_count_compacted -= (target_compacted_count - this_compacted_count);
brw_inst_set_gen6_jump_count(brw, insn, jump_count_compacted);
brw_inst_set_gen6_jump_count(devinfo, insn, jump_count_compacted);
} else {
update_gen4_jump_count(brw, insn, this_old_ip, compacted_counts);
}
@ -1489,20 +1498,20 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
* and Gens that use this cannot compact instructions with immediate
* operands.
*/
if (brw_inst_cmpt_control(brw, insn))
if (brw_inst_cmpt_control(devinfo, insn))
break;
if (brw_inst_dst_reg_file(brw, insn) == BRW_ARCHITECTURE_REGISTER_FILE &&
brw_inst_dst_da_reg_nr(brw, insn) == BRW_ARF_IP) {
assert(brw_inst_src1_reg_file(brw, insn) == BRW_IMMEDIATE_VALUE);
if (brw_inst_dst_reg_file(devinfo, insn) == BRW_ARCHITECTURE_REGISTER_FILE &&
brw_inst_dst_da_reg_nr(devinfo, insn) == BRW_ARF_IP) {
assert(brw_inst_src1_reg_file(devinfo, insn) == BRW_IMMEDIATE_VALUE);
int shift = 3;
int jump_compacted = brw_inst_imm_d(brw, insn) >> shift;
int jump_compacted = brw_inst_imm_d(devinfo, insn) >> shift;
int target_old_ip = this_old_ip + (jump_compacted / 2);
int target_compacted_count = compacted_counts[target_old_ip];
jump_compacted -= (target_compacted_count - this_compacted_count);
brw_inst_set_imm_ud(brw, insn, jump_compacted << shift);
brw_inst_set_imm_ud(devinfo, insn, jump_compacted << shift);
}
break;
}
@ -1529,12 +1538,12 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
sizeof(brw_inst) != annotation[i].offset) {
assert(start_offset + old_ip[offset / sizeof(brw_compact_inst)] *
sizeof(brw_inst) < annotation[i].offset);
offset = next_offset(brw, store, offset);
offset = next_offset(devinfo, store, offset);
}
annotation[i].offset = start_offset + offset;
offset = next_offset(brw, store, offset);
offset = next_offset(devinfo, store, offset);
}
annotation[num_annotations].offset = p->next_insn_offset;

998
src/mesa/drivers/dri/i965/brw_eu_emit.c
View file

File diff suppressed because it is too large Load diff

7
src/mesa/drivers/dri/i965/brw_ff_gs_emit.c
View file

@ -346,7 +346,6 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
unsigned num_verts, bool check_edge_flags)
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
brw_inst *inst;
c->prog_data.svbi_postincrement_value = num_verts;
@ -412,7 +411,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
inst = brw_MOV(p, destination_indices_uw,
brw_imm_v(key->pv_first ? 0x00010200 /* (0, 2, 1) */
: 0x00020001)); /* (1, 0, 2) */
brw_inst_set_pred_control(brw, inst, BRW_PREDICATE_NORMAL);
brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL);
}
brw_ADD(p, c->reg.destination_indices,
c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
@ -502,7 +501,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
get_element_ud(c->reg.R0, 2),
brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
}
brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
@ -518,7 +517,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
get_element_ud(c->reg.R0, 2),
brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
}
brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);

54
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -164,7 +164,7 @@ fs_generator::patch_discard_jumps_to_fb_writes()
if (brw->gen < 6 || this->discard_halt_patches.is_empty())
return false;
int scale = brw_jump_scale(brw);
int scale = brw_jump_scale(p->devinfo);
/* There is a somewhat strange undocumented requirement of using
* HALT, according to the simulator. If some channel has HALTed to
@ -178,17 +178,17 @@ fs_generator::patch_discard_jumps_to_fb_writes()
* tests.
*/
brw_inst *last_halt = gen6_HALT(p);
brw_inst_set_uip(brw, last_halt, 1 * scale);
brw_inst_set_jip(brw, last_halt, 1 * scale);
brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
int ip = p->nr_insn;
foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
brw_inst *patch = &p->store[patch_ip->ip];
assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
/* HALT takes a half-instruction distance from the pre-incremented IP. */
brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
}
this->discard_halt_patches.make_empty();
@ -337,10 +337,10 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
v1_null_ud,
retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
brw_imm_ud(1<<26));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
{
/* Don't send AA data */
fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
@ -361,14 +361,14 @@ fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
brw_set_src0(p, insn, payload);
brw_set_src1(p, insn, brw_imm_d(0));
brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
brw_inst_set_mlen(brw, insn, inst->mlen);
brw_inst_set_rlen(brw, insn, 0);
brw_inst_set_eot(brw, insn, inst->eot);
brw_inst_set_header_present(brw, insn, true);
brw_inst_set_urb_global_offset(brw, insn, inst->offset);
brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
brw_inst_set_rlen(p->devinfo, insn, 0);
brw_inst_set_eot(p->devinfo, insn, inst->eot);
brw_inst_set_header_present(p->devinfo, insn, true);
brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
}
void
@ -793,8 +793,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
}
if (is_combined_send) {
brw_inst_set_eot(brw, brw_last_inst, true);
brw_inst_set_opcode(brw, brw_last_inst, BRW_OPCODE_SENDC);
brw_inst_set_eot(p->devinfo, brw_last_inst, true);
brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
}
}
@ -1091,7 +1091,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
/* a0.0 = surf_index & 0xff */
brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
brw_set_dest(p, insn_and, addr);
brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
@ -1162,11 +1162,11 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
gen6_resolve_implied_move(p, &header, inst->base_mrf);
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
brw_set_src0(p, send, header);
if (brw->gen < 6)
brw_inst_set_base_mrf(brw, send, inst->base_mrf);
brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
/* Our surface is set up as floats, regardless of what actual data is
* stored in it.
@ -1239,7 +1239,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
/* a0.0 = surf_index & 0xff */
brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
brw_set_dest(p, insn_and, addr);
brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
@ -1658,8 +1658,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
if (inst->conditional_mod) {
brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
multiple_instructions_emitted = true;
}
} else {
@ -1680,8 +1680,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
if (inst->conditional_mod) {
brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
multiple_instructions_emitted = true;
}
} else {
@ -2115,9 +2115,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
brw_inst *last = &p->store[last_insn_offset / 16];
if (inst->conditional_mod)
brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
}
}

140
src/mesa/drivers/dri/i965/brw_inst.h
View file

@ -52,19 +52,19 @@ static inline void brw_inst_set_bits(brw_inst *inst,
#define FC(name, high, low, assertions) \
static inline void \
brw_inst_set_##name(const struct brw_context *brw, \
brw_inst_set_##name(const struct brw_device_info *devinfo, \
brw_inst *inst, uint64_t v) \
{ \
assert(assertions); \
(void) brw; \
(void) devinfo; \
brw_inst_set_bits(inst, high, low, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct brw_context *brw, \
brw_inst_##name(const struct brw_device_info *devinfo, \
const brw_inst *inst) \
{ \
assert(assertions); \
(void) brw; \
(void) devinfo; \
return brw_inst_bits(inst, high, low); \
}
@ -73,15 +73,15 @@ brw_inst_##name(const struct brw_context *brw, \
#define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
unsigned high, low; \
if (brw->gen >= 8) { \
if (devinfo->gen >= 8) { \
high = hi8; low = lo8; \
} else if (brw->gen >= 7) { \
} else if (devinfo->gen >= 7) { \
high = hi7; low = lo7; \
} else if (brw->gen >= 6) { \
} else if (devinfo->gen >= 6) { \
high = hi6; low = lo6; \
} else if (brw->gen >= 5) { \
} else if (devinfo->gen >= 5) { \
high = hi5; low = lo5; \
} else if (brw->is_g4x) { \
} else if (devinfo->is_g4x) { \
high = hi45; low = lo45; \
} else { \
high = hi4; low = lo4; \
@ -94,14 +94,14 @@ brw_inst_##name(const struct brw_context *brw, \
*/
#define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
static inline void \
brw_inst_set_##name(const struct brw_context *brw, \
brw_inst_set_##name(const struct brw_device_info *devinfo, \
brw_inst *inst, uint64_t value) \
{ \
BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
brw_inst_set_bits(inst, high, low, value); \
} \
static inline uint64_t \
brw_inst_##name(const struct brw_context *brw, const brw_inst *inst) \
brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
{ \
BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
return brw_inst_bits(inst, high, low); \
@ -171,10 +171,10 @@ F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
F(saturate, 31, 31)
F(debug_control, 30, 30)
F(cmpt_control, 29, 29)
FC(branch_control, 28, 28, brw->gen >= 8)
FC(branch_control, 28, 28, devinfo->gen >= 8)
F(acc_wr_control, 28, 28)
F(cond_modifier, 27, 24)
FC(math_function, 27, 24, brw->gen >= 6)
FC(math_function, 27, 24, devinfo->gen >= 6)
F(exec_size, 23, 21)
F(pred_inv, 20, 20)
F(pred_control, 19, 16)
@ -247,12 +247,12 @@ F(3src_opcode, 6, 0)
* @{
*/
static inline void
brw_inst_set_uip(const struct brw_context *brw,
brw_inst_set_uip(const struct brw_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(brw->gen >= 6);
assert(devinfo->gen >= 6);
if (brw->gen >= 8) {
if (devinfo->gen >= 8) {
brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
} else {
assert(value <= (1 << 16) - 1);
@ -262,11 +262,11 @@ brw_inst_set_uip(const struct brw_context *brw,
}
static inline int32_t
brw_inst_uip(const struct brw_context *brw, const brw_inst *inst)
brw_inst_uip(const struct brw_device_info *devinfo, const brw_inst *inst)
{
assert(brw->gen >= 6);
assert(devinfo->gen >= 6);
if (brw->gen >= 8) {
if (devinfo->gen >= 8) {
return brw_inst_bits(inst, 95, 64);
} else {
return (int16_t)brw_inst_bits(inst, 127, 112);
@ -274,12 +274,12 @@ brw_inst_uip(const struct brw_context *brw, const brw_inst *inst)
}
static inline void
brw_inst_set_jip(const struct brw_context *brw,
brw_inst_set_jip(const struct brw_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(brw->gen >= 6);
assert(devinfo->gen >= 6);
if (brw->gen >= 8) {
if (devinfo->gen >= 8) {
brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
} else {
assert(value <= (1 << 16) - 1);
@ -289,11 +289,11 @@ brw_inst_set_jip(const struct brw_context *brw,
}
static inline int32_t
brw_inst_jip(const struct brw_context *brw, const brw_inst *inst)
brw_inst_jip(const struct brw_device_info *devinfo, const brw_inst *inst)
{
assert(brw->gen >= 6);
assert(devinfo->gen >= 6);
if (brw->gen >= 8) {
if (devinfo->gen >= 8) {
return brw_inst_bits(inst, 127, 96);
} else {
return (int16_t)brw_inst_bits(inst, 111, 96);
@ -303,23 +303,23 @@ brw_inst_jip(const struct brw_context *brw, const brw_inst *inst)
/** Like FC, but using int16_t to handle negative jump targets. */
#define FJ(name, high, low, assertions) \
static inline void \
brw_inst_set_##name(const struct brw_context *brw, brw_inst *inst, int16_t v) \
brw_inst_set_##name(const struct brw_device_info *devinfo, brw_inst *inst, int16_t v) \
{ \
assert(assertions); \
(void) brw; \
(void) devinfo; \
brw_inst_set_bits(inst, high, low, (uint16_t) v); \
} \
static inline int16_t \
brw_inst_##name(const struct brw_context *brw, const brw_inst *inst) \
brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
{ \
assert(assertions); \
(void) brw; \
(void) devinfo; \
return brw_inst_bits(inst, high, low); \
}
FJ(gen6_jump_count, 63, 48, brw->gen == 6)
FJ(gen4_jump_count, 111, 96, brw->gen < 6)
FC(gen4_pop_count, 115, 112, brw->gen < 6)
FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
/** @} */
/**
@ -361,7 +361,7 @@ FF(sfid,
/* 6: */ 27, 24,
/* 7: */ 27, 24,
/* 8: */ 27, 24)
FC(base_mrf, 27, 24, brw->gen < 6);
FC(base_mrf, 27, 24, devinfo->gen < 6);
/** @} */
/* Message descriptor bits */
@ -375,9 +375,9 @@ FF(urb_per_slot_offset,
/* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
/* 7: */ MD(16), MD(16),
/* 8: */ MD(17), MD(17))
FC(urb_complete, MD(15), MD(15), brw->gen < 8)
FC(urb_used, MD(14), MD(14), brw->gen < 7)
FC(urb_allocate, MD(13), MD(13), brw->gen < 7)
FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
FF(urb_swizzle_control,
/* 4: */ MD(11), MD(10),
/* 4.5: */ MD(11), MD(10),
@ -405,11 +405,11 @@ FF(urb_opcode,
* Gen4-5 math messages:
* @{
*/
FC(math_msg_data_type, MD(7), MD(7), brw->gen < 6)
FC(math_msg_saturate, MD(6), MD(6), brw->gen < 6)
FC(math_msg_precision, MD(5), MD(5), brw->gen < 6)
FC(math_msg_signed_int, MD(4), MD(4), brw->gen < 6)
FC(math_msg_function, MD(3), MD(0), brw->gen < 6)
FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
/** @} */
/**
@ -429,7 +429,7 @@ FF(sampler_msg_type,
/* 6: */ MD(15), MD(12),
/* 7: */ MD(16), MD(12),
/* 8: */ MD(16), MD(12))
FC(sampler_return_format, MD(13), MD(12), brw->gen == 4 && !brw->is_g4x)
FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
F(sampler, MD(11), MD(8))
F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
/** @} */
@ -438,7 +438,7 @@ F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
* Data port message function control bits:
* @{
*/
FC(dp_category, MD(18), MD(18), brw->gen >= 7)
FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
/* Gen4-5 store fields in different bits for read/write messages. */
FF(dp_read_msg_type,
@ -469,7 +469,7 @@ FF(dp_write_msg_control,
/* 6: */ MD(12), MD( 8),
/* 7: */ MD(13), MD( 8),
/* 8: */ MD(13), MD( 8))
FC(dp_read_target_cache, MD(15), MD(14), brw->gen < 6);
FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
FF(dp_write_commit,
/* 4: */ MD(15), MD(15),
@ -497,11 +497,11 @@ FF(dp_msg_control,
* Scratch message bits (Gen7+):
* @{
*/
FC(scratch_read_write, MD(17), MD(17), brw->gen >= 7) /* 0 = read, 1 = write */
FC(scratch_type, MD(16), MD(16), brw->gen >= 7) /* 0 = OWord, 1 = DWord */
FC(scratch_invalidate_after_read, MD(15), MD(15), brw->gen >= 7)
FC(scratch_block_size, MD(13), MD(12), brw->gen >= 7)
FC(scratch_addr_offset, MD(11), MD( 0), brw->gen >= 7)
FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
/** @} */
/**
@ -515,7 +515,7 @@ FF(rt_last,
/* 6: */ MD(12), MD(12),
/* 7: */ MD(12), MD(12),
/* 8: */ MD(12), MD(12))
FC(rt_slot_group, MD(11), MD(11), brw->gen >= 6)
FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
F(rt_message_type, MD(10), MD( 8))
/** @} */
@ -544,50 +544,50 @@ F(pi_message_data, MD(7), MD(0))
* @{
*/
static inline int
brw_inst_imm_d(const struct brw_context *brw, const brw_inst *insn)
brw_inst_imm_d(const struct brw_device_info *devinfo, const brw_inst *insn)
{
(void) brw;
(void) devinfo;
return brw_inst_bits(insn, 127, 96);
}
static inline unsigned
brw_inst_imm_ud(const struct brw_context *brw, const brw_inst *insn)
brw_inst_imm_ud(const struct brw_device_info *devinfo, const brw_inst *insn)
{
(void) brw;
(void) devinfo;
return brw_inst_bits(insn, 127, 96);
}
static inline float
brw_inst_imm_f(const struct brw_context *brw, const brw_inst *insn)
brw_inst_imm_f(const struct brw_device_info *devinfo, const brw_inst *insn)
{
fi_type ft;
(void) brw;
(void) devinfo;
ft.u = brw_inst_bits(insn, 127, 96);
return ft.f;
}
static inline void
brw_inst_set_imm_d(const struct brw_context *brw,
brw_inst_set_imm_d(const struct brw_device_info *devinfo,
brw_inst *insn, int value)
{
(void) brw;
(void) devinfo;
return brw_inst_set_bits(insn, 127, 96, value);
}
static inline void
brw_inst_set_imm_ud(const struct brw_context *brw,
brw_inst_set_imm_ud(const struct brw_device_info *devinfo,
brw_inst *insn, unsigned value)
{
(void) brw;
(void) devinfo;
return brw_inst_set_bits(insn, 127, 96, value);
}
static inline void
brw_inst_set_imm_f(const struct brw_context *brw,
brw_inst_set_imm_f(const struct brw_device_info *devinfo,
brw_inst *insn, float value)
{
fi_type ft;
(void) brw;
(void) devinfo;
ft.f = value;
brw_inst_set_bits(insn, 127, 96, ft.u);
}
@ -597,12 +597,12 @@ brw_inst_set_imm_f(const struct brw_context *brw,
/* The AddrImm fields are split into two discontiguous sections on Gen8+ */
#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
static inline void \
brw_inst_set_##reg##_ia1_addr_imm(const struct brw_context *brw, \
brw_inst_set_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
brw_inst *inst, \
unsigned value) \
{ \
assert((value & ~0x3ff) == 0); \
if (brw->gen >= 8) { \
if (devinfo->gen >= 8) { \
brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
} else { \
@ -610,10 +610,10 @@ brw_inst_set_##reg##_ia1_addr_imm(const struct brw_context *brw, \
} \
} \
static inline unsigned \
brw_inst_##reg##_ia1_addr_imm(const struct brw_context *brw, \
brw_inst_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (brw->gen >= 8) { \
if (devinfo->gen >= 8) { \
return brw_inst_bits(inst, g8_high, g8_low) | \
(brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
} else { \
@ -629,11 +629,11 @@ BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
#define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
static inline void \
brw_inst_set_##reg##_ia16_addr_imm(const struct brw_context *brw, \
brw_inst_set_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
brw_inst *inst, unsigned value) \
{ \
assert((value & ~0x3ff) == 0); \
if (brw->gen >= 8) { \
if (devinfo->gen >= 8) { \
brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
} else { \
@ -641,10 +641,10 @@ brw_inst_set_##reg##_ia16_addr_imm(const struct brw_context *brw, \
} \
} \
static inline unsigned \
brw_inst_##reg##_ia16_addr_imm(const struct brw_context *brw, \
brw_inst_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (brw->gen >= 8) { \
if (devinfo->gen >= 8) { \
return brw_inst_bits(inst, g8_high, g8_low) | \
(brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
} else { \

4
src/mesa/drivers/dri/i965/brw_reg.h
View file

@ -53,7 +53,7 @@
extern "C" {
#endif
struct brw_context;
struct brw_device_info;
/** Number of general purpose registers (VS, WM, etc) */
#define BRW_MAX_GRF 128
@ -218,7 +218,7 @@ enum PACKED brw_reg_type {
BRW_REGISTER_TYPE_Q,
};
unsigned brw_reg_type_to_hw_type(const struct brw_context *brw,
unsigned brw_reg_type_to_hw_type(const struct brw_device_info *devinfo,
enum brw_reg_type type, unsigned file);
const char *brw_reg_type_letters(unsigned brw_reg_type);

7
src/mesa/drivers/dri/i965/brw_sf_emit.c
View file

@ -730,7 +730,6 @@ void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate)
void brw_emit_anyprim_setup( struct brw_sf_compile *c )
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0);
struct brw_reg payload_attr = get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0);
struct brw_reg primmask;
@ -752,7 +751,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_POLYGON) |
(1<<_3DPRIM_RECTLIST) |
(1<<_3DPRIM_TRIFAN_NOSTIPPLE)));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_tri_setup(c, false);
brw_land_fwd_jump(p, jmp);
@ -763,13 +762,13 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_LINESTRIP_CONT) |
(1<<_3DPRIM_LINESTRIP_BF) |
(1<<_3DPRIM_LINESTRIP_CONT_BF)));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_line_setup(c, false);
brw_land_fwd_jump(p, jmp);
brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<<BRW_SPRITE_POINT_ENABLE));
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_point_sprite_setup(c, false);
brw_land_fwd_jump(p, jmp);

28
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View file

@ -901,7 +901,7 @@ vec4_generator::generate_scratch_read(vec4_instruction *inst,
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (brw->gen < 6)
brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
brw_set_dp_read_message(p, send,
255, /* binding table index: stateless access */
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@ -972,7 +972,7 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst,
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (brw->gen < 6)
brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
brw_set_dp_write_message(p, send,
255, /* binding table index: stateless access */
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@ -1018,7 +1018,7 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (brw->gen < 6)
brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
brw_set_dp_read_message(p, send,
surf_index,
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@ -1066,7 +1066,7 @@ vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
/* a0.0 = surf_index & 0xff */
brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
brw_set_dest(p, insn_and, addr);
brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
@ -1339,7 +1339,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
brw_inst_set_pred_control(brw, if_inst, inst->predicate);
brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
}
break;
@ -1553,16 +1553,16 @@ vec4_generator::generate_code(const cfg_t *cfg)
src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
dst.subnr = offset * 4;
struct brw_inst *insn = brw_MOV(p, dst, src[0]);
brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
brw_inst_set_no_dd_clear(brw, insn, true);
brw_inst_set_no_dd_check(brw, insn, inst->no_dd_check);
brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
src[0].subnr = 16;
dst.subnr = 16 + offset * 4;
insn = brw_MOV(p, dst, src[0]);
brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
brw_inst_set_no_dd_clear(brw, insn, inst->no_dd_clear);
brw_inst_set_no_dd_check(brw, insn, true);
brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
brw_inst_set_no_dd_check(p->devinfo, insn, true);
brw_set_default_access_mode(p, BRW_ALIGN_16);
break;
@ -1590,9 +1590,9 @@ vec4_generator::generate_code(const cfg_t *cfg)
brw_inst *last = &p->store[pre_emit_nr_insn];
if (inst->conditional_mod)
brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
}
}

36
src/mesa/drivers/dri/i965/test_eu_compact.c
View file

@ -67,20 +67,20 @@ test_compact_instruction(struct brw_compile *p, brw_inst src)
* become meaningless once fuzzing twiddles a related bit.
*/
static void
clear_pad_bits(const struct brw_context *brw, brw_inst *inst)
clear_pad_bits(const struct brw_device_info *devinfo, brw_inst *inst)
{
if (brw_inst_opcode(brw, inst) != BRW_OPCODE_SEND &&
brw_inst_opcode(brw, inst) != BRW_OPCODE_SENDC &&
brw_inst_opcode(brw, inst) != BRW_OPCODE_BREAK &&
brw_inst_opcode(brw, inst) != BRW_OPCODE_CONTINUE &&
brw_inst_src0_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE) {
if (brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SEND &&
brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SENDC &&
brw_inst_opcode(devinfo, inst) != BRW_OPCODE_BREAK &&
brw_inst_opcode(devinfo, inst) != BRW_OPCODE_CONTINUE &&
brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
brw_inst_set_bits(inst, 127, 111, 0);
}
}
static bool
skip_bit(const struct brw_context *brw, brw_inst *src, int bit)
skip_bit(const struct brw_device_info *devinfo, brw_inst *src, int bit)
{
/* pad bit */
if (bit == 7)
@ -99,12 +99,12 @@ skip_bit(const struct brw_context *brw, brw_inst *src, int bit)
return true;
/* sometimes these are pad bits. */
if (brw_inst_opcode(brw, src) != BRW_OPCODE_SEND &&
brw_inst_opcode(brw, src) != BRW_OPCODE_SENDC &&
brw_inst_opcode(brw, src) != BRW_OPCODE_BREAK &&
brw_inst_opcode(brw, src) != BRW_OPCODE_CONTINUE &&
brw_inst_src0_reg_file(brw, src) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_reg_file(brw, src) != BRW_IMMEDIATE_VALUE &&
if (brw_inst_opcode(devinfo, src) != BRW_OPCODE_SEND &&
brw_inst_opcode(devinfo, src) != BRW_OPCODE_SENDC &&
brw_inst_opcode(devinfo, src) != BRW_OPCODE_BREAK &&
brw_inst_opcode(devinfo, src) != BRW_OPCODE_CONTINUE &&
brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
bit >= 121) {
return true;
}
@ -116,20 +116,20 @@ static bool
test_fuzz_compact_instruction(struct brw_compile *p, brw_inst src)
{
for (int bit0 = 0; bit0 < 128; bit0++) {
if (skip_bit(p->brw, &src, bit0))
if (skip_bit(p->devinfo, &src, bit0))
continue;
for (int bit1 = 0; bit1 < 128; bit1++) {
brw_inst instr = src;
uint32_t *bits = (uint32_t *)&instr;
if (skip_bit(p->brw, &src, bit1))
if (skip_bit(p->devinfo, &src, bit1))
continue;
bits[bit0 / 32] ^= (1 << (bit0 & 31));
bits[bit1 / 32] ^= (1 << (bit1 & 31));
clear_pad_bits(p->brw, &instr);
clear_pad_bits(p->devinfo, &instr);
if (!test_compact_instruction(p, instr)) {
printf(" twiddled bits for fuzzing %d, %d\n", bit0, bit1);
@ -233,7 +233,7 @@ gen_f0_1_MOV_GRF_GRF(struct brw_compile *p)
brw_push_insn_state(p);
brw_set_default_predicate_control(p, true);
brw_inst *mov = brw_MOV(p, g0, g2);
brw_inst_set_flag_subreg_nr(p->brw, mov, 1);
brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
brw_pop_insn_state(p);
}