fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-29 18:50:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

iris: make the TFB result visible to others

Browse source 
OpenGL 4.6 Spec:
   "5.3.3 Rules
    .......
    Note: “Updates” via rendering or transform feedback
    are treated consistently with updates via GL commands.
    Once EndTransformFeedback has been issued, any subsequent
    command in the same context that uses the results of the
    transform feedback operation will see the results."

v2: removed a wrong comment
    ( Kenneth Graunke <kenneth@whitecape.org> )

v3: - flush+dirty depends on buffers usage history
    - removed an old hack
    ( Kenneth Graunke <kenneth@whitecape.org> )

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110404
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Andrii Simiklit 2019-04-25 11:19:46 +03:00 • committed by Kenneth Graunke
parent aa7306b4cf
commit 4e9592c5fa
1 changed files with 15 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

25
src/gallium/drivers/iris/iris_state.c
View file

@ -2954,8 +2954,22 @@ iris_set_stream_output_targets(struct pipe_context *ctx,
* may have missed emitting it earlier, so do so now. (We're already
* taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
*/
if (active)
if (active) {
ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST;
} else {
uint32_t flush = 0;
for (int i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
struct iris_stream_output_target *tgt =
(void *) ice->state.so_target[i];
if (tgt) {
struct iris_resource *res = (void *) tgt->base.buffer;
flush |= iris_flush_bits_for_history(res);
iris_dirty_for_history(ice, res);
}
}
iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_RENDER], flush);
}
}
for (int i = 0; i < 4; i++) {
@ -4980,15 +4994,6 @@ iris_upload_dirty_render_state(struct iris_context *ice,
PIPE_CONTROL_CS_STALL;
ice->state.last_vbo_high_bits[i] = high_bits;
}
/* If the buffer was written to by streamout, we may need
* to stall so those writes land and become visible to the
* vertex fetcher.
*
* TODO: This may stall more than necessary.
*/
if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
flush_flags |= PIPE_CONTROL_CS_STALL;
}
}