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pan/midgard: Partially fix 64-bit swizzle alignment

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When mixing 32/64-bit, we need to align the 32-bit registers to get the
required alignment. This isn't quite enough yet, though, since user
swizzles could bypass and will need to be lowered to 32-bit moves
(outstanding todo).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
This commit is contained in:
Alyssa Rosenzweig 2020-02-27 09:15:00 -05:00 • committed by Marge Bot
parent 9c59f9f379
commit 4e60dc8f48
2 changed files with 24 additions and 3 deletions
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12
src/panfrost/midgard/midgard_emit.c
View file

@ -196,11 +196,17 @@ mir_pack_swizzle_alu(midgard_instruction *ins)
if (mode == midgard_reg_mode_32) {
bool lo = ins->swizzle[i][0] >= COMPONENT_Z;
bool hi = ins->swizzle[i][1] >= COMPONENT_Z;
unsigned mask = mir_bytemask(ins);
/* TODO: can we mix halves? */
assert(lo == hi);
if (mask & 0xFF) {
/* We can't mix halves... */
if (mask & 0xFF00)
assert(lo == hi);
src[i].rep_low |= lo;
src[i].rep_low |= lo;
} else {
src[i].rep_low |= hi;
}
} else if (mode < midgard_reg_mode_32) {
unreachable("Cannot encode 8/16 swizzle in 64-bit");
}

15
src/panfrost/midgard/midgard_ra.c
View file

@ -477,6 +477,21 @@ allocate_registers(compiler_context *ctx, bool *spilled)
unsigned *min_alignment = calloc(sizeof(unsigned), ctx->temp_count);
mir_foreach_instr_global(ctx, ins) {
/* Swizzles of 32-bit sources on 64-bit instructions need to be
* aligned to either bottom (xy) or top (zw). More general
* swizzle lowering should happen prior to scheduling (TODO),
* but once we get RA we shouldn't disrupt this further. Align
* sources of 64-bit instructions. */
if (ins->type == TAG_ALU_4 && ins->alu.reg_mode == midgard_reg_mode_64) {
mir_foreach_src(ins, v) {
unsigned s = ins->src[v];
if (s < ctx->temp_count)
min_alignment[s] = 3;
}
}
if (ins->dest >= SSA_FIXED_MINIMUM) continue;
/* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */