From 4e06a8f15e0de36babcf9910db088cc3c42efd61 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 30 Jun 2022 18:14:23 +0800 Subject: [PATCH] nir: add nir_intrinsic_ordered_xfb_counter_add_amd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Timur Kristóf Signed-off-by: Qiang Yu Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 1fe64c930ca..867cbb5ff82 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -631,6 +631,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_btd_stack_id_intel: case nir_intrinsic_load_topology_id_intel: case nir_intrinsic_load_scratch_base_ptr: + case nir_intrinsic_ordered_xfb_counter_add_amd: is_divergent = true; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 92c6adbbed9..71ae27bb4c7 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1434,6 +1434,11 @@ intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[3 # An ID for each workgroup ordered by primitve sequence system_value("ordered_id_amd", 1) +# Add to global streamout buffer counter in specified order +# src[] = { ordered_id, counter } +# WRITE_MASK = mask for counter channel to update +intrinsic("ordered_xfb_counter_add_amd", dest_comp=0, src_comp=[1, 0], indices=[WRITE_MASK], bit_sizes=[32]) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel