diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 0f52b48d27b..9f97af2f882 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1424,8 +1424,13 @@ blorp_emit_surface_state(struct blorp_batch *batch,
       /* We can't reinterpret HiZ */
       assert(surface->surf.format == surface->view.format);
    }
+
    enum isl_aux_usage aux_usage = surface->aux_usage;
 
+   /* On gen12, implicit CCS has no aux buffer */
+   bool use_aux_address = (aux_usage != ISL_AUX_USAGE_NONE) &&
+                          (surface->aux_addr.buffer != NULL);
+
    isl_channel_mask_t write_disable_mask = 0;
    if (is_render_target && GEN_GEN <= 5) {
       if (color_write_disables[0])
@@ -1446,7 +1451,7 @@ blorp_emit_surface_state(struct blorp_batch *batch,
                        .aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
                        .address =
                           blorp_get_surface_address(batch, surface->addr),
-                       .aux_address = aux_usage == ISL_AUX_USAGE_NONE ? 0 :
+                       .aux_address = use_aux_address ? 0 :
                           blorp_get_surface_address(batch, surface->aux_addr),
                        .clear_address = !use_clear_address ? 0 :
                           blorp_get_surface_address(batch,
@@ -1459,7 +1464,7 @@ blorp_emit_surface_state(struct blorp_batch *batch,
    blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
                        surface->addr, 0);
 
-   if (aux_usage != ISL_AUX_USAGE_NONE) {
+   if (use_aux_address) {
       /* On gen7 and prior, the bottom 12 bits of the MCS base address are
        * used to store other information.  This should be ok, however, because
        * surface buffer addresses are always 4K page alinged.