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i965/fs: Fix the clock increment in scheduling.

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I've tested this to be true with various ALU ops on gen7 (with the
exception of MADs, which go at either 3 or 4 cycles per dispatch).

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt 2012-12-05 16:17:58 -08:00
parent 6255fc7426
commit 4df1e18864
1 changed files with 15 additions and 3 deletions
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18
src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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@ -553,10 +553,22 @@ instruction_scheduler::schedule_instructions(fs_inst *next_block_header)
next_block_header->insert_before(chosen->inst);
instructions_to_schedule--;
/* Bump the clock. If we expected a delay for scheduling, then
* bump the clock to reflect that.
/* Bump the clock. Instructions in gen hardware are handled one simd4
* vector at a time, with 1 cycle per vector dispatched. Thus 8-wide
* pixel shaders take 2 cycles to dispatch and 16-wide (compressed)
* instructions take 4.
*/
time = MAX2(time + 1, chosen_time);
if (is_compressed(chosen->inst))
time += 4;
else
time += 2;
/* If we expected a delay for scheduling, then bump the clock to reflect
* that as well. In reality, the hardware will switch to another
* hyperthread and may not return to dispatching our thread for a while
* even after we're unblocked.
*/
time = MAX2(time, chosen_time);
if (debug) {
printf("clock %4d, scheduled: ", time);