nir: change intel dss_id intrinsic to topology_id

This will allow to reuse the same intrinsic for various topology based
ID.

v2: fix intrinsic comment (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

src/compiler/nir/nir_intrinsics.py

@@ -1353,7 +1353,8 @@ store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET])
 system_value("mesh_inline_data_intel", 1, [ALIGN_OFFSET], bit_sizes=[32, 64])
 
 # Intrinsics for Intel bindless thread dispatch
-system_value("btd_dss_id_intel", 1)
+# BASE=brw_topoloy_id
+system_value("topology_id_intel", 1, indices=[BASE])
 system_value("btd_stack_id_intel", 1)
 system_value("btd_global_arg_addr_intel", 1, bit_sizes=[64])
 system_value("btd_local_arg_addr_intel", 1, bit_sizes=[64])

src/compiler/nir/nir_lower_shader_calls.c

@@ -163,7 +163,7 @@ can_remat_instr(nir_instr *instr, struct brw_bitset *remat)
 
       case nir_intrinsic_load_scratch_base_ptr:
       case nir_intrinsic_load_ray_launch_id:
-      case nir_intrinsic_load_btd_dss_id_intel:
+      case nir_intrinsic_load_topology_id_intel:
       case nir_intrinsic_load_btd_global_arg_addr_intel:
       case nir_intrinsic_load_btd_resume_sbt_addr_intel:
       case nir_intrinsic_load_ray_base_mem_addr_intel:

src/intel/compiler/brw_compiler.h

@@ -2007,6 +2007,21 @@ brw_compute_first_urb_slot_required(uint64_t inputs_read,
 #define BRW_TASK_MESH_PUSH_CONSTANTS_SIZE_DW \
    (BRW_TASK_MESH_INLINE_DATA_SIZE_DW - BRW_TASK_MESH_PUSH_CONSTANTS_START_DW)
 
+/**
+ * This enum is used as the base indice of the nir_load_topology_id_intel
+ * intrinsic. This is used to return different values based on some aspect of
+ * the topology of the device.
+ */
+enum brw_topology_id
+{
+   /* A value based of the DSS identifier the shader is currently running on.
+    * Be mindful that the DSS ID can be higher than the total number of DSS on
+    * the device. This is because of the fusing that can occur on different
+    * parts.
+    */
+   BRW_TOPOLOGY_ID_DSS,
+};
+
 #ifdef __cplusplus
 } /* extern "C" */
 #endif

src/intel/compiler/brw_fs_nir.cpp

@@ -5727,7 +5727,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
       break;
    }
 
-   case nir_intrinsic_load_btd_dss_id_intel:
+   case nir_intrinsic_load_topology_id_intel:
+      assert(nir_intrinsic_base(instr) == BRW_TOPOLOGY_ID_DSS);
       bld.emit(SHADER_OPCODE_GET_DSS_ID,
                retype(dest, BRW_REGISTER_TYPE_UD));
       break;

src/intel/compiler/brw_nir_rt_builder.h

@@ -27,6 +27,12 @@
 #include "brw_rt.h"
 #include "nir_builder.h"
 
+static inline nir_ssa_def *
+brw_load_btd_dss_id(nir_builder *b)
+{
+   return nir_build_load_topology_id_intel(b, .base = BRW_TOPOLOGY_ID_DSS);
+}
+
 /* We have our own load/store scratch helpers because they emit a global
  * memory read or write based on the scratch_base_ptr system value rather
  * than a load/store_scratch intrinsic.
@@ -97,7 +103,7 @@ static inline nir_ssa_def *
 brw_nir_rt_stack_id(nir_builder *b)
 {
    return nir_iadd(b, nir_umul_32x16(b, nir_load_ray_num_dss_rt_stacks_intel(b),
-                                     nir_load_btd_dss_id_intel(b)),
+                                        brw_load_btd_dss_id(b)),
                       nir_load_btd_stack_id_intel(b));
 }