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radv/meta: remove unused number of rectangles for internal operations

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It was always 1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30187>
This commit is contained in:
Samuel Pitoiset 2024-07-12 17:15:43 +02:00 • committed by Marge Bot
parent ecd3bbf826
commit 4deb138e7d
5 changed files with 196 additions and 218 deletions
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16
src/amd/vulkan/meta/radv_meta.h
View file

@ -196,23 +196,20 @@ struct radv_meta_blit2d_rect {
void radv_meta_begin_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_saved_state *save);
void radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src_img,
struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst, unsigned num_rects,
struct radv_meta_blit2d_rect *rects);
struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst,
struct radv_meta_blit2d_rect *rect);
void radv_meta_end_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_saved_state *save);
VkResult radv_device_init_meta_bufimage_state(struct radv_device *device);
void radv_device_finish_meta_bufimage_state(struct radv_device *device);
void radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
struct radv_meta_blit2d_buffer *dst, unsigned num_rects,
struct radv_meta_blit2d_rect *rects);
struct radv_meta_blit2d_buffer *dst, struct radv_meta_blit2d_rect *rect);
void radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_buffer *src,
struct radv_meta_blit2d_surf *dst, unsigned num_rects,
struct radv_meta_blit2d_rect *rects);
struct radv_meta_blit2d_surf *dst, struct radv_meta_blit2d_rect *rect);
void radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
struct radv_meta_blit2d_surf *dst, unsigned num_rects,
struct radv_meta_blit2d_rect *rects);
struct radv_meta_blit2d_surf *dst, struct radv_meta_blit2d_rect *rect);
void radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *dst,
const VkClearColorValue *clear_color);
@ -233,8 +230,7 @@ void radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_v
struct radv_image *dst_image, struct radv_buffer *htile_buffer, bool read_htile_value);
bool radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image,
const struct radv_image *dst_image, unsigned num_rects,
const struct radv_meta_blit2d_rect *rects);
const struct radv_image *dst_image, const struct radv_meta_blit2d_rect *rect);
void radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
struct radv_meta_blit2d_surf *dst);

280
src/amd/vulkan/meta/radv_meta_blit2d.c
View file

@ -161,185 +161,181 @@ bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer, enum blit2d_src_type s
static void
radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src_img,
struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst,
unsigned num_rects, struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type,
uint32_t log2_samples)
struct radv_meta_blit2d_rect *rect, enum blit2d_src_type src_type, uint32_t log2_samples)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
for (unsigned r = 0; r < num_rects; ++r) {
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
&(VkViewport){.x = rects[r].dst_x,
.y = rects[r].dst_y,
.width = rects[r].width,
.height = rects[r].height,
.minDepth = 0.0f,
.maxDepth = 1.0f});
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
&(VkViewport){.x = rect->dst_x,
.y = rect->dst_y,
.width = rect->width,
.height = rect->height,
.minDepth = 0.0f,
.maxDepth = 1.0f});
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
&(VkRect2D){
.offset = (VkOffset2D){rects[r].dst_x, rects[r].dst_y},
.extent = (VkExtent2D){rects[r].width, rects[r].height},
});
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
&(VkRect2D){
.offset = (VkOffset2D){rect->dst_x, rect->dst_y},
.extent = (VkExtent2D){rect->width, rect->height},
});
u_foreach_bit (i, dst->aspect_mask) {
unsigned aspect_mask = 1u << i;
unsigned src_aspect_mask = aspect_mask;
VkFormat depth_format = 0;
if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
depth_format = vk_format_stencil_only(dst->image->vk.format);
else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
depth_format = vk_format_depth_only(dst->image->vk.format);
else if (src_img)
src_aspect_mask = src_img->aspect_mask;
u_foreach_bit (i, dst->aspect_mask) {
unsigned aspect_mask = 1u << i;
unsigned src_aspect_mask = aspect_mask;
VkFormat depth_format = 0;
if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
depth_format = vk_format_stencil_only(dst->image->vk.format);
else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
depth_format = vk_format_depth_only(dst->image->vk.format);
else if (src_img)
src_aspect_mask = src_img->aspect_mask;
struct blit2d_src_temps src_temps;
blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, src_aspect_mask,
log2_samples);
struct blit2d_src_temps src_temps;
blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, src_aspect_mask, log2_samples);
struct radv_image_view dst_iview;
create_iview(cmd_buffer, dst, &dst_iview, depth_format, aspect_mask);
struct radv_image_view dst_iview;
create_iview(cmd_buffer, dst, &dst_iview, depth_format, aspect_mask);
float vertex_push_constants[4] = {
rects[r].src_x,
rects[r].src_y,
rects[r].src_x + rects[r].width,
rects[r].src_y + rects[r].height,
float vertex_push_constants[4] = {
rect->src_x,
rect->src_y,
rect->src_x + rect->width,
rect->src_y + rect->height,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
VK_SHADER_STAGE_VERTEX_BIT, 0, 16, vertex_push_constants);
if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT || aspect_mask == VK_IMAGE_ASPECT_PLANE_0_BIT ||
aspect_mask == VK_IMAGE_ASPECT_PLANE_1_BIT || aspect_mask == VK_IMAGE_ASPECT_PLANE_2_BIT) {
unsigned fs_key = radv_format_meta_fs_key(device, dst_iview.vk.format);
if (device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key] == VK_NULL_HANDLE) {
VkResult ret =
blit2d_init_color_pipeline(device, src_type, radv_fs_key_format_exemplars[fs_key], log2_samples);
if (ret != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
goto fail_pipeline;
}
}
const VkRenderingAttachmentInfo color_att_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
.imageView = radv_image_view_to_handle(&dst_iview),
.imageLayout = dst->current_layout,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
VK_SHADER_STAGE_VERTEX_BIT, 0, 16, vertex_push_constants);
const VkRenderingInfo rendering_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
.renderArea =
{
.offset = {rect->dst_x, rect->dst_y},
.extent = {rect->width, rect->height},
},
.layerCount = 1,
.colorAttachmentCount = 1,
.pColorAttachments = &color_att_info,
};
if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT || aspect_mask == VK_IMAGE_ASPECT_PLANE_0_BIT ||
aspect_mask == VK_IMAGE_ASPECT_PLANE_1_BIT || aspect_mask == VK_IMAGE_ASPECT_PLANE_2_BIT) {
unsigned fs_key = radv_format_meta_fs_key(device, dst_iview.vk.format);
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
if (device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key] == VK_NULL_HANDLE) {
VkResult ret =
blit2d_init_color_pipeline(device, src_type, radv_fs_key_format_exemplars[fs_key], log2_samples);
if (ret != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
goto fail_pipeline;
}
bind_pipeline(cmd_buffer, src_type, fs_key, log2_samples);
} else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
if (device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type] == VK_NULL_HANDLE) {
VkResult ret = blit2d_init_depth_only_pipeline(device, src_type, log2_samples);
if (ret != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
goto fail_pipeline;
}
}
const VkRenderingAttachmentInfo color_att_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
.imageView = radv_image_view_to_handle(&dst_iview),
.imageLayout = dst->current_layout,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
};
const VkRenderingAttachmentInfo depth_att_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
.imageView = radv_image_view_to_handle(&dst_iview),
.imageLayout = dst->current_layout,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
};
const VkRenderingInfo rendering_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
.renderArea =
{
.offset = {rects[r].dst_x, rects[r].dst_y},
.extent = {rects[r].width, rects[r].height},
},
.layerCount = 1,
.colorAttachmentCount = 1,
.pColorAttachments = &color_att_info,
};
const VkRenderingInfo rendering_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
.renderArea =
{
.offset = {rect->dst_x, rect->dst_y},
.extent = {rect->width, rect->height},
},
.layerCount = 1,
.pDepthAttachment = &depth_att_info,
.pStencilAttachment = (dst->image->vk.aspects & VK_IMAGE_ASPECT_STENCIL_BIT) ? &depth_att_info : NULL,
};
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
bind_pipeline(cmd_buffer, src_type, fs_key, log2_samples);
} else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
if (device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type] == VK_NULL_HANDLE) {
VkResult ret = blit2d_init_depth_only_pipeline(device, src_type, log2_samples);
if (ret != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
goto fail_pipeline;
}
bind_depth_pipeline(cmd_buffer, src_type, log2_samples);
} else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
if (device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type] == VK_NULL_HANDLE) {
VkResult ret = blit2d_init_stencil_only_pipeline(device, src_type, log2_samples);
if (ret != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
goto fail_pipeline;
}
}
const VkRenderingAttachmentInfo depth_att_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
.imageView = radv_image_view_to_handle(&dst_iview),
.imageLayout = dst->current_layout,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
};
const VkRenderingAttachmentInfo stencil_att_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
.imageView = radv_image_view_to_handle(&dst_iview),
.imageLayout = dst->current_layout,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
};
const VkRenderingInfo rendering_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
.renderArea =
{
.offset = {rects[r].dst_x, rects[r].dst_y},
.extent = {rects[r].width, rects[r].height},
},
.layerCount = 1,
.pDepthAttachment = &depth_att_info,
.pStencilAttachment = (dst->image->vk.aspects & VK_IMAGE_ASPECT_STENCIL_BIT) ? &depth_att_info : NULL,
};
const VkRenderingInfo rendering_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
.renderArea =
{
.offset = {rect->dst_x, rect->dst_y},
.extent = {rect->width, rect->height},
},
.layerCount = 1,
.pDepthAttachment = (dst->image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ? &stencil_att_info : NULL,
.pStencilAttachment = &stencil_att_info,
};
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
bind_depth_pipeline(cmd_buffer, src_type, log2_samples);
bind_stencil_pipeline(cmd_buffer, src_type, log2_samples);
} else
unreachable("Processing blit2d with multiple aspects.");
} else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
if (device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type] == VK_NULL_HANDLE) {
VkResult ret = blit2d_init_stencil_only_pipeline(device, src_type, log2_samples);
if (ret != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
goto fail_pipeline;
}
}
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
const VkRenderingAttachmentInfo stencil_att_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
.imageView = radv_image_view_to_handle(&dst_iview),
.imageLayout = dst->current_layout,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
};
radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
const VkRenderingInfo rendering_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
.renderArea =
{
.offset = {rects[r].dst_x, rects[r].dst_y},
.extent = {rects[r].width, rects[r].height},
},
.layerCount = 1,
.pDepthAttachment = (dst->image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ? &stencil_att_info : NULL,
.pStencilAttachment = &stencil_att_info,
};
fail_pipeline:
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
if (src_type == BLIT2D_SRC_TYPE_BUFFER)
radv_buffer_view_finish(&src_temps.bview);
else
radv_image_view_finish(&src_temps.iview);
bind_stencil_pipeline(cmd_buffer, src_type, log2_samples);
} else
unreachable("Processing blit2d with multiple aspects.");
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
fail_pipeline:
if (src_type == BLIT2D_SRC_TYPE_BUFFER)
radv_buffer_view_finish(&src_temps.bview);
else
radv_image_view_finish(&src_temps.iview);
radv_image_view_finish(&dst_iview);
}
radv_image_view_finish(&dst_iview);
}
}
void
radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src_img,
struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst, unsigned num_rects,
struct radv_meta_blit2d_rect *rects)
struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst,
struct radv_meta_blit2d_rect *rect)
{
bool use_3d = (src_img && src_img->image->vk.image_type == VK_IMAGE_TYPE_3D);
enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER
: use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D
: BLIT2D_SRC_TYPE_IMAGE;
radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst, num_rects, rects, src_type,
radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst, rect, src_type,
src_img ? util_logbase2(src_img->image->vk.samples) : 0);
}

98
src/amd/vulkan/meta/radv_meta_bufimage.c
View file

@ -1276,7 +1276,7 @@ itob_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view
void
radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
struct radv_meta_blit2d_buffer *dst, unsigned num_rects, struct radv_meta_blit2d_rect *rects)
struct radv_meta_blit2d_buffer *dst, struct radv_meta_blit2d_rect *rect)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
VkPipeline pipeline = device->meta_state.itob.pipeline;
@ -1292,14 +1292,12 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_b
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
for (unsigned r = 0; r < num_rects; ++r) {
unsigned push_constants[4] = {rects[r].src_x, rects[r].src_y, src->layer, dst->pitch};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itob.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants);
unsigned push_constants[4] = {rect->src_x, rect->src_y, src->layer, dst->pitch};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itob.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants);
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
fixup_gfx9_cs_copy(cmd_buffer, dst, src, &rects[r], false);
}
radv_unaligned_dispatch(cmd_buffer, rect->width, rect->height, 1);
fixup_gfx9_cs_copy(cmd_buffer, dst, src, rect, false);
radv_image_view_finish(&src_view);
radv_buffer_view_finish(&dst_view);
@ -1333,8 +1331,7 @@ btoi_r32g32b32_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, struct radv_
static void
radv_meta_buffer_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_buffer *src,
struct radv_meta_blit2d_surf *dst, unsigned num_rects,
struct radv_meta_blit2d_rect *rects)
struct radv_meta_blit2d_surf *dst, struct radv_meta_blit2d_rect *rect)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
VkPipeline pipeline = device->meta_state.btoi_r32g32b32.pipeline;
@ -1357,19 +1354,17 @@ radv_meta_buffer_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struc
stride = get_image_stride_for_r32g32b32(cmd_buffer, dst);
for (unsigned r = 0; r < num_rects; ++r) {
unsigned push_constants[4] = {
rects[r].dst_x,
rects[r].dst_y,
stride,
src->pitch,
};
unsigned push_constants[4] = {
rect->dst_x,
rect->dst_y,
stride,
src->pitch,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi_r32g32b32.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants);
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi_r32g32b32.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants);
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
}
radv_unaligned_dispatch(cmd_buffer, rect->width, rect->height, 1);
radv_buffer_view_finish(&src_view);
radv_buffer_view_finish(&dst_view);
@ -1407,7 +1402,7 @@ btoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer_vie
void
radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_buffer *src,
struct radv_meta_blit2d_surf *dst, unsigned num_rects, struct radv_meta_blit2d_rect *rects)
struct radv_meta_blit2d_surf *dst, struct radv_meta_blit2d_rect *rect)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
VkPipeline pipeline = device->meta_state.btoi.pipeline;
@ -1416,7 +1411,7 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_met
if (dst->image->vk.format == VK_FORMAT_R32G32B32_UINT || dst->image->vk.format == VK_FORMAT_R32G32B32_SINT ||
dst->image->vk.format == VK_FORMAT_R32G32B32_SFLOAT) {
radv_meta_buffer_to_image_cs_r32g32b32(cmd_buffer, src, dst, num_rects, rects);
radv_meta_buffer_to_image_cs_r32g32b32(cmd_buffer, src, dst, rect);
return;
}
@ -1428,19 +1423,17 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_met
pipeline = device->meta_state.btoi.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
for (unsigned r = 0; r < num_rects; ++r) {
unsigned push_constants[4] = {
rects[r].dst_x,
rects[r].dst_y,
dst->layer,
src->pitch,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants);
unsigned push_constants[4] = {
rect->dst_x,
rect->dst_y,
dst->layer,
src->pitch,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants);
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
fixup_gfx9_cs_copy(cmd_buffer, src, dst, &rects[r], true);
}
radv_unaligned_dispatch(cmd_buffer, rect->width, rect->height, 1);
fixup_gfx9_cs_copy(cmd_buffer, src, dst, rect, true);
radv_image_view_finish(&dst_view);
radv_buffer_view_finish(&src_view);
@ -1474,8 +1467,7 @@ itoi_r32g32b32_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, struct radv_
static void
radv_meta_image_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
struct radv_meta_blit2d_surf *dst, unsigned num_rects,
struct radv_meta_blit2d_rect *rects)
struct radv_meta_blit2d_surf *dst, struct radv_meta_blit2d_rect *rect)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
VkPipeline pipeline = device->meta_state.itoi_r32g32b32.pipeline;
@ -1504,15 +1496,13 @@ radv_meta_image_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struct
src_stride = get_image_stride_for_r32g32b32(cmd_buffer, src);
dst_stride = get_image_stride_for_r32g32b32(cmd_buffer, dst);
for (unsigned r = 0; r < num_rects; ++r) {
unsigned push_constants[6] = {
rects[r].src_x, rects[r].src_y, src_stride, rects[r].dst_x, rects[r].dst_y, dst_stride,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi_r32g32b32.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants);
unsigned push_constants[6] = {
rect->src_x, rect->src_y, src_stride, rect->dst_x, rect->dst_y, dst_stride,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi_r32g32b32.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants);
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
}
radv_unaligned_dispatch(cmd_buffer, rect->width, rect->height, 1);
radv_buffer_view_finish(&src_view);
radv_buffer_view_finish(&dst_view);
@ -1555,7 +1545,7 @@ itoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view
void
radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
struct radv_meta_blit2d_surf *dst, unsigned num_rects, struct radv_meta_blit2d_rect *rects)
struct radv_meta_blit2d_surf *dst, struct radv_meta_blit2d_rect *rect)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_image_view src_view, dst_view;
@ -1564,7 +1554,7 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta
if (src->format == VK_FORMAT_R32G32B32_UINT || src->format == VK_FORMAT_R32G32B32_SINT ||
src->format == VK_FORMAT_R32G32B32_SFLOAT) {
radv_meta_image_to_image_cs_r32g32b32(cmd_buffer, src, dst, num_rects, rects);
radv_meta_image_to_image_cs_r32g32b32(cmd_buffer, src, dst, rect);
return;
}
@ -1602,15 +1592,13 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
for (unsigned r = 0; r < num_rects; ++r) {
unsigned push_constants[6] = {
rects[r].src_x, rects[r].src_y, src->layer, rects[r].dst_x, rects[r].dst_y, dst->layer,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants);
unsigned push_constants[6] = {
rect->src_x, rect->src_y, src->layer, rect->dst_x, rect->dst_y, dst->layer,
};
vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi.img_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants);
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
}
radv_unaligned_dispatch(cmd_buffer, rect->width, rect->height, 1);
radv_image_view_finish(&src_view);
radv_image_view_finish(&dst_view);

12
src/amd/vulkan/meta/radv_meta_copy.c
View file

@ -196,9 +196,9 @@ copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
/* Perform Blit */
if (cs) {
radv_meta_buffer_to_image_cs(cmd_buffer, &buf_bsurf, &img_bsurf, 1, &rect);
radv_meta_buffer_to_image_cs(cmd_buffer, &buf_bsurf, &img_bsurf, &rect);
} else {
radv_meta_blit2d(cmd_buffer, NULL, &buf_bsurf, &img_bsurf, 1, &rect);
radv_meta_blit2d(cmd_buffer, NULL, &buf_bsurf, &img_bsurf, &rect);
}
/* Once we've done the blit, all of the actual information about
@ -345,7 +345,7 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
rect.src_y = img_offset_el.y;
/* Perform Blit */
radv_meta_image_to_buffer(cmd_buffer, &img_info, &buf_info, 1, &rect);
radv_meta_image_to_buffer(cmd_buffer, &img_info, &buf_info, &rect);
buf_info.offset += buf_extent_el.width * buf_extent_el.height * buf_info.bs;
img_info.layer++;
@ -560,12 +560,12 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, VkI
/* Perform Blit */
if (cs) {
radv_meta_image_to_image_cs(cmd_buffer, &b_src, &b_dst, 1, &rect);
radv_meta_image_to_image_cs(cmd_buffer, &b_src, &b_dst, &rect);
} else {
if (radv_can_use_fmask_copy(cmd_buffer, b_src.image, b_dst.image, 1, &rect)) {
if (radv_can_use_fmask_copy(cmd_buffer, b_src.image, b_dst.image, &rect)) {
radv_fmask_copy(cmd_buffer, &b_src, &b_dst);
} else {
radv_meta_blit2d(cmd_buffer, &b_src, NULL, &b_dst, 1, &rect);
radv_meta_blit2d(cmd_buffer, &b_src, NULL, &b_dst, &rect);
}
}

8
src/amd/vulkan/meta/radv_meta_fmask_copy.c
View file

@ -212,8 +212,7 @@ radv_fixup_copy_dst_metadata(struct radv_cmd_buffer *cmd_buffer, const struct ra
bool
radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image,
const struct radv_image *dst_image, unsigned num_rects,
const struct radv_meta_blit2d_rect *rects)
const struct radv_image *dst_image, const struct radv_meta_blit2d_rect *rect)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
@ -235,9 +234,8 @@ radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, const struct radv_im
return false;
/* The region must be a whole image copy. */
if (num_rects != 1 ||
(rects[0].src_x || rects[0].src_y || rects[0].dst_x || rects[0].dst_y ||
rects[0].width != src_image->vk.extent.width || rects[0].height != src_image->vk.extent.height))
if (rect->src_x || rect->src_y || rect->dst_x || rect->dst_y || rect->width != src_image->vk.extent.width ||
rect->height != src_image->vk.extent.height)
return false;
/* Source/destination images must have identical size. */