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radv: allow to select DST_SEL with RELEASE_MEM

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Samuel Pitoiset 2019-07-12 18:12:34 +02:00
parent 3c6d6bd71f
commit 4dcdc4cdc5
4 changed files with 11 additions and 3 deletions
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2
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -5397,6 +5397,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->device->physical_device->rad_info.chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM,
EOP_DATA_SEL_VALUE_32BIT, va, value,
cmd_buffer->gfx9_eop_bug_va);
}
@ -5808,6 +5809,7 @@ void radv_CmdWriteBufferMarkerAMD(
cmd_buffer->device->physical_device->rad_info.chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM,
EOP_DATA_SEL_VALUE_32BIT,
va, marker,
cmd_buffer->gfx9_eop_bug_va);

2
src/amd/vulkan/radv_private.h
View file

@ -1244,7 +1244,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
bool is_mec,
unsigned event, unsigned event_flags,
unsigned data_sel,
unsigned dst_sel, unsigned data_sel,
uint64_t va,
uint32_t new_fence,
uint64_t gfx9_eop_bug_va);

2
src/amd/vulkan/radv_query.c
View file

@ -1619,6 +1619,7 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->device->physical_device->rad_info.chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM,
EOP_DATA_SEL_VALUE_32BIT,
avail_va, 1,
cmd_buffer->gfx9_eop_bug_va);
@ -1763,6 +1764,7 @@ void radv_CmdWriteTimestamp(
cmd_buffer->device->physical_device->rad_info.chip_class,
mec,
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM,
EOP_DATA_SEL_TIMESTAMP,
query_va, 0,
cmd_buffer->gfx9_eop_bug_va);

8
src/amd/vulkan/si_cmd_buffer.c
View file

@ -759,7 +759,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
bool is_mec,
unsigned event, unsigned event_flags,
unsigned data_sel,
unsigned dst_sel, unsigned data_sel,
uint64_t va,
uint32_t new_fence,
uint64_t gfx9_eop_bug_va)
@ -769,7 +769,8 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
event == V_028A90_PS_DONE ? 6 : 5) |
event_flags;
unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
unsigned sel = EOP_DATA_SEL(data_sel);
unsigned sel = EOP_DST_SEL(dst_sel) |
EOP_DATA_SEL(data_sel);
/* Wait for write confirmation before writing data, but don't send
* an interrupt. */
@ -988,6 +989,7 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
S_490_GL2_INV(gl2_inv) |
S_490_GL2_WB(gl2_wb) |
S_490_SEQ(gcr_seq),
EOP_DST_SEL_MEM,
EOP_DATA_SEL_VALUE_32BIT,
flush_va, *flush_cnt,
gfx9_eop_bug_va);
@ -1075,6 +1077,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
is_mec,
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
0,
EOP_DST_SEL_MEM,
EOP_DATA_SEL_DISCARD,
0, 0,
gfx9_eop_bug_va);
@ -1146,6 +1149,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
(*flush_cnt)++;
si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
EOP_DST_SEL_MEM,
EOP_DATA_SEL_VALUE_32BIT,
flush_va, *flush_cnt,
gfx9_eop_bug_va);