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nak/sm32: Encode surface address ops
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34975>
This commit is contained in:
Lorenzo Rossi
Marge Bot
parent
2c0d0bad01
commit
4d86f95cff
1 changed files with 286 additions and 1 deletions
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@ -2196,6 +2196,285 @@ impl SM32Op for OpTxq {
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}
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}
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impl SM32Op for OpSuClamp {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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b.copy_alu_src_if_not_reg(&mut self.coords, GPR, SrcType::ALU);
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b.copy_alu_src_if_i20_overflow(&mut self.params, GPR, SrcType::ALU);
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}
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fn encode(&self, e: &mut SM32Encoder<'_>) {
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e.encode_form_immreg(
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0xb00,
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0x180,
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Some(&self.dst),
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&self.coords,
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&self.params,
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None,
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false,
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);
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e.set_field(42..48, self.imm);
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e.set_pred_dst(48..51, &self.out_of_bounds);
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e.set_bit(51, self.is_s32);
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let round = match self.round {
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SuClampRound::R1 => 0,
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SuClampRound::R2 => 1,
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SuClampRound::R4 => 2,
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SuClampRound::R8 => 3,
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SuClampRound::R16 => 4,
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};
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let mode = match self.mode {
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SuClampMode::StoredInDescriptor => 0_u8,
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SuClampMode::PitchLinear => 5,
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SuClampMode::BlockLinear => 10,
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};
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e.set_field(52..56, mode + round);
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e.set_bit(56, self.is_2d); // .1d
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}
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}
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impl SM32Op for OpSuBfm {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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b.copy_alu_src_if_not_reg(&mut self.srcs[0], GPR, SrcType::ALU);
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b.copy_alu_src_if_i20_overflow(&mut self.srcs[1], GPR, SrcType::ALU);
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b.copy_alu_src_if_not_reg(&mut self.srcs[2], GPR, SrcType::ALU);
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}
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fn encode(&self, e: &mut SM32Encoder<'_>) {
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e.encode_form_immreg(
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0xb68,
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0x1e8,
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Some(&self.dst),
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&self.srcs[0],
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&self.srcs[1],
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Some(&self.srcs[2]),
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false,
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);
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e.set_bit(50, self.is_3d);
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e.set_pred_dst(51..54, &self.pdst);
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}
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}
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impl SM32Op for OpSuEau {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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b.copy_alu_src_if_not_reg(&mut self.off, GPR, SrcType::ALU);
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b.copy_alu_src_if_i20_overflow(&mut self.bit_field, GPR, SrcType::ALU);
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b.copy_alu_src_if_not_reg(&mut self.addr, GPR, SrcType::ALU);
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}
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fn encode(&self, e: &mut SM32Encoder<'_>) {
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e.encode_form_immreg(
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0xb6c,
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0x1ec,
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Some(&self.dst),
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&self.off,
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&self.bit_field,
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Some(&self.addr),
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false,
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);
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}
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}
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impl SM32Op for OpIMadSp {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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let [src0, src1, src2] = &mut self.srcs;
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b.copy_alu_src_if_not_reg(src0, GPR, SrcType::ALU);
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b.copy_alu_src_if_i20_overflow(src1, GPR, SrcType::ALU);
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b.copy_alu_src_if_not_reg(src2, GPR, SrcType::ALU);
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}
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fn encode(&self, e: &mut SM32Encoder<'_>) {
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e.encode_form_immreg(
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0xa40,
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0x140,
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Some(&self.dst),
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&self.srcs[0],
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&self.srcs[1],
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Some(&self.srcs[2]),
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false,
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);
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match self.mode {
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IMadSpMode::Explicit([src0, src1, src2]) => {
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use IMadSpSrcType::*;
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assert!(
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src2.sign() == (src1.sign() || src0.sign()),
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"Cannot encode imadsp signed combination"
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);
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e.set_bit(51, src0.sign());
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e.set_field(
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52..54,
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match src0.unsigned() {
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U32 => 0_u8,
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U24 => 1,
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U16Lo => 2,
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U16Hi => 3,
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_ => unreachable!(),
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},
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);
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e.set_field(
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54..56,
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match src2.unsigned() {
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U32 => 0_u8,
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U24 => 1,
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U16Lo => 2,
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U16Hi => {
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panic!("src2 u16h1 not encodable")
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}
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_ => unreachable!(),
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},
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);
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e.set_bit(56, src1.sign());
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// Don't trust nvdisasm on this, this is inverted
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e.set_field(
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57..58,
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match src1.unsigned() {
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U24 => 1_u8,
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U16Lo => 0,
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_ => panic!("imadsp src[1] can only be 16 or 24 bits"),
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},
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);
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}
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IMadSpMode::FromSrc1 => {
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e.set_field(54..56, 3_u8);
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}
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}
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}
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}
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impl SM32Encoder<'_> {
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fn set_su_ga_offset_mode(
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&mut self,
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range: Range<usize>,
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off_type: SuGaOffsetMode,
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) {
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assert!(range.len() == 2);
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self.set_field(
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range,
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match off_type {
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SuGaOffsetMode::U32 => 0_u8,
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SuGaOffsetMode::S32 => 1_u8,
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SuGaOffsetMode::U8 => 2_u8,
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SuGaOffsetMode::S8 => 3_u8,
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},
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);
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}
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}
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impl SM32Op for OpSuLdGa {
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fn legalize(&mut self, _b: &mut LegalizeBuilder) {}
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fn encode(&self, e: &mut SM32Encoder<'_>) {
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match &self.format.src_ref {
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SrcRef::CBuf(cb) => {
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e.set_opcode(0x300, 2);
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e.set_mem_type(56..59, self.mem_type);
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// 54..56 cache hints (.ca, .cg, .cs, .cv)
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e.set_src_cbuf(23..42, &cb);
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}
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SrcRef::Zero | SrcRef::Reg(_) => {
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e.set_opcode(0x798, 2);
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e.set_mem_type(33..36, self.mem_type);
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// 31..33 cache hints (.ca, .cg, .cs, .cv)
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e.set_reg_src(23..31, &self.format);
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}
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_ => panic!("Unhandled format src type"),
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}
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// surface pred: 42..46
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e.set_pred_src(42..46, &self.out_of_bounds);
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// Surface clamp:
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// 0: zero
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// 1: trap
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// 3: sdcl
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e.set_field(46..48, 0_u8);
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e.set_su_ga_offset_mode(52..54, self.offset_mode);
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e.set_dst(&self.dst);
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// address
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e.set_reg_src(10..18, &self.addr);
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}
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}
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impl SM32Op for OpSuStGa {
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fn legalize(&mut self, _b: &mut LegalizeBuilder) {}
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fn encode(&self, e: &mut SM32Encoder<'_>) {
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match &self.format.src_ref {
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SrcRef::CBuf(cb) => {
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e.set_opcode(0x380, 2);
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// Surface clamp: [ignore, trap, invalid, sdcl]
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e.set_field(2..4, 0_u8);
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match self.image_access {
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ImageAccess::Binary(mem_type) => {
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e.set_field(4..8, 0); // channel mask
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e.set_mem_type(56..59, mem_type); // mem_type
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}
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ImageAccess::Formatted(mask) => {
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e.set_field(4..8, mask.to_bits()); // channel mask
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e.set_field(56..59, 0_u8); // mem_type
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}
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};
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e.set_su_ga_offset_mode(8..10, self.offset_mode);
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e.set_src_cbuf(23..42, &cb);
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// 54..56 cache hints (.wb, .cg, .cs, .wt)
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}
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SrcRef::Zero | SrcRef::Reg(_) => {
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e.set_opcode(0x79c, 2);
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e.set_reg_src(2..10, &self.format);
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// Surface clamp: [ignore, trap, invalid, sdcl]
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e.set_field(23..25, 0_u8);
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match self.image_access {
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ImageAccess::Binary(mem_type) => {
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e.set_field(25..29, 0); // channel mask
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e.set_mem_type(33..36, mem_type); // mem_type
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}
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ImageAccess::Formatted(mask) => {
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e.set_field(25..29, mask.to_bits()); // channel mask
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e.set_field(33..36, 0_u8); // mem_type
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}
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};
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e.set_su_ga_offset_mode(29..31, self.offset_mode);
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// 31..33 cache hints (.wb, ??, .cs, .wt)
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}
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_ => panic!("Unhandled format src type"),
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}
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// out_of_bounds pred
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e.set_pred_src(50..54, &self.out_of_bounds);
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// address
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e.set_reg_src(10..18, &self.addr);
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e.set_reg_src(42..50, &self.data);
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}
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}
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/// Helper to legalize extended or external instructions
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///
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/// These are instructions which reach out external units such as load/store
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@ -2995,7 +3274,7 @@ impl SM32Op for OpOut {
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}
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}
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// TODO: instructions left behind from codegen rewrite,
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// Instructions left behind from codegen rewrite,
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// we might use them in the future:
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// - 0x138 pret.noinc
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// - 0x1b8 quadon (enable all threads in quad)
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@ -3046,6 +3325,12 @@ macro_rules! as_sm50_op_match {
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Op::Tmml(op) => op,
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Op::Txd(op) => op,
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Op::Txq(op) => op,
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Op::SuClamp(op) => op,
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Op::SuBfm(op) => op,
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Op::SuEau(op) => op,
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Op::IMadSp(op) => op,
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Op::SuLdGa(op) => op,
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Op::SuStGa(op) => op,
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Op::Ld(op) => op,
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Op::Ldc(op) => op,
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Op::LdSharedLock(op) => op,
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