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radv: cleanup passing the aspect mask for SDMA operations
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Less error prone than it used to be.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34143>
This commit is contained in:
Samuel Pitoiset 2025-03-19 12:01:12 +01:00 • committed by Marge Bot
parent e60cafa533
commit 4d68875acd
3 changed files with 24 additions and 29 deletions
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21
src/amd/vulkan/meta/radv_meta_copy.c
View file

@ -80,11 +80,9 @@ transfer_copy_memory_image(struct radv_cmd_buffer *cmd_buffer, uint64_t buffer_v
{
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radeon_cmdbuf *cs = cmd_buffer->cs;
const VkImageAspectFlags aspect_mask = region->imageSubresource.aspectMask;
struct radv_sdma_surf buf = radv_sdma_get_buf_surf(buffer_va, image, region);
const struct radv_sdma_surf img =
radv_sdma_get_surf(device, image, region->imageSubresource, region->imageOffset, aspect_mask);
const struct radv_sdma_surf img = radv_sdma_get_surf(device, image, region->imageSubresource, region->imageOffset);
const VkExtent3D extent = radv_sdma_get_copy_extent(image, region->imageSubresource, region->imageExtent);
if (radv_sdma_use_unaligned_buffer_image_copy(device, &buf, &img, extent)) {
@ -395,15 +393,16 @@ transfer_copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_i
struct radeon_cmdbuf *cs = cmd_buffer->cs;
unsigned int dst_aspect_mask_remaining = region->dstSubresource.aspectMask;
u_foreach_bit (b, region->srcSubresource.aspectMask) {
const VkImageAspectFlags src_aspect_mask = BITFIELD_BIT(b);
const VkImageAspectFlags dst_aspect_mask = BITFIELD_BIT(u_bit_scan(&dst_aspect_mask_remaining));
VkImageSubresourceLayers src_subresource = region->srcSubresource;
VkImageSubresourceLayers dst_subresource = region->dstSubresource;
const struct radv_sdma_surf src =
radv_sdma_get_surf(device, src_image, region->srcSubresource, region->srcOffset, src_aspect_mask);
const struct radv_sdma_surf dst =
radv_sdma_get_surf(device, dst_image, region->dstSubresource, region->dstOffset, dst_aspect_mask);
const VkExtent3D extent = radv_sdma_get_copy_extent(src_image, region->srcSubresource, region->extent);
u_foreach_bit (b, region->srcSubresource.aspectMask) {
src_subresource.aspectMask = BITFIELD_BIT(b);
dst_subresource.aspectMask = BITFIELD_BIT(u_bit_scan(&dst_aspect_mask_remaining));
const struct radv_sdma_surf src = radv_sdma_get_surf(device, src_image, src_subresource, region->srcOffset);
const struct radv_sdma_surf dst = radv_sdma_get_surf(device, dst_image, dst_subresource, region->dstOffset);
const VkExtent3D extent = radv_sdma_get_copy_extent(src_image, src_subresource, region->extent);
if (radv_sdma_use_t2t_scanline_copy(device, &src, &dst, extent)) {
if (!alloc_transfer_temp_bo(cmd_buffer))

29
src/amd/vulkan/radv_sdma.c
View file

@ -191,8 +191,7 @@ radv_sdma_get_buf_surf(uint64_t buffer_va, const struct radv_image *const image,
static uint32_t
radv_sdma_get_metadata_config(const struct radv_device *const device, const struct radv_image *const image,
const struct radeon_surf *const surf, const VkImageSubresourceLayers subresource,
const VkImageAspectFlags aspect_mask)
const struct radeon_surf *const surf, const VkImageSubresourceLayers subresource)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
@ -201,13 +200,13 @@ radv_sdma_get_metadata_config(const struct radv_device *const device, const stru
return 0;
}
const VkFormat format = vk_format_get_aspect_format(image->vk.format, aspect_mask);
const VkFormat format = vk_format_get_aspect_format(image->vk.format, subresource.aspectMask);
const struct util_format_description *desc = vk_format_description(format);
const uint32_t data_format = ac_get_cb_format(pdev->info.gfx_level, radv_format_to_pipe_format(format));
const uint32_t alpha_is_on_msb = ac_alpha_is_on_msb(&pdev->info, radv_format_to_pipe_format(format));
const uint32_t number_type = radv_translate_buffer_numformat(desc, vk_format_get_first_non_void_channel(format));
const uint32_t surface_type = radv_sdma_surface_type_from_aspect_mask(aspect_mask);
const uint32_t surface_type = radv_sdma_surface_type_from_aspect_mask(subresource.aspectMask);
const uint32_t max_comp_block_size = surf->u.gfx9.color.dcc.max_compressed_block_size;
const uint32_t max_uncomp_block_size = radv_get_dcc_max_uncompressed_block_size(device, image);
const uint32_t pipe_aligned = radv_htile_enabled(image, subresource.mipLevel) || surf->u.gfx9.color.dcc.pipe_aligned;
@ -218,11 +217,10 @@ radv_sdma_get_metadata_config(const struct radv_device *const device, const stru
static uint32_t
radv_sdma_get_tiled_info_dword(const struct radv_device *const device, const struct radv_image *const image,
const struct radeon_surf *const surf, const VkImageSubresourceLayers subresource,
const VkImageAspectFlags aspect_mask)
const struct radeon_surf *const surf, const VkImageSubresourceLayers subresource)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const uint32_t bpe = radv_sdma_get_bpe(image, aspect_mask);
const uint32_t bpe = radv_sdma_get_bpe(image, subresource.aspectMask);
const uint32_t element_size = util_logbase2(bpe);
const uint32_t swizzle_mode = surf->has_stencil ? surf->u.gfx9.zs.stencil_swizzle_mode : surf->u.gfx9.swizzle_mode;
const enum gfx9_resource_type dimension = radv_sdma_surface_resource_type(device, surf);
@ -262,17 +260,16 @@ radv_sdma_get_tiled_header_dword(const struct radv_device *const device, const s
struct radv_sdma_surf
radv_sdma_get_surf(const struct radv_device *const device, const struct radv_image *const image,
const VkImageSubresourceLayers subresource, const VkOffset3D offset,
const VkImageAspectFlags aspect_mask)
const VkImageSubresourceLayers subresource, const VkOffset3D offset)
{
assert(util_bitcount(aspect_mask) == 1);
assert(util_bitcount(subresource.aspectMask) == 1);
const struct radv_physical_device *pdev = radv_device_physical(device);
const unsigned plane_idx = radv_plane_from_aspect(aspect_mask);
const unsigned plane_idx = radv_plane_from_aspect(subresource.aspectMask);
const unsigned binding_idx = image->disjoint ? plane_idx : 0;
const struct radeon_surf *const surf = &image->planes[plane_idx].surface;
const uint64_t va = image->bindings[binding_idx].addr;
const uint32_t bpe = radv_sdma_get_bpe(image, aspect_mask);
const uint32_t bpe = radv_sdma_get_bpe(image, subresource.aspectMask);
struct radv_sdma_surf info = {
.extent =
{
@ -295,8 +292,8 @@ radv_sdma_get_surf(const struct radv_device *const device, const struct radv_ima
.is_3d = surf->u.gfx9.resource_type == RADEON_RESOURCE_3D,
};
const uint64_t surf_offset =
(aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) ? surf->u.gfx9.zs.stencil_offset : surf->u.gfx9.surf_offset;
const uint64_t surf_offset = (subresource.aspectMask == VK_IMAGE_ASPECT_STENCIL_BIT) ? surf->u.gfx9.zs.stencil_offset
: surf->u.gfx9.surf_offset;
if (surf->is_linear) {
info.va = va + surf_offset + surf->u.gfx9.offset[subresource.mipLevel];
@ -308,13 +305,13 @@ radv_sdma_get_surf(const struct radv_device *const device, const struct radv_ima
info.va = (va + surf_offset) | surf->tile_swizzle << 8;
info.info_dword = radv_sdma_get_tiled_info_dword(device, image, surf, subresource, aspect_mask);
info.info_dword = radv_sdma_get_tiled_info_dword(device, image, surf, subresource);
info.header_dword = radv_sdma_get_tiled_header_dword(device, image, subresource);
if (pdev->info.sdma_supports_compression &&
(radv_dcc_enabled(image, subresource.mipLevel) || radv_htile_enabled(image, subresource.mipLevel))) {
info.meta_va = va + surf->meta_offset;
info.meta_config = radv_sdma_get_metadata_config(device, image, surf, subresource, aspect_mask);
info.meta_config = radv_sdma_get_metadata_config(device, image, surf, subresource);
}
}

3
src/amd/vulkan/radv_sdma.h
View file

@ -54,8 +54,7 @@ radv_sdma_get_copy_extent(const struct radv_image *const image, const VkImageSub
struct radv_sdma_surf radv_sdma_get_buf_surf(uint64_t buffer_va, const struct radv_image *const image,
const VkBufferImageCopy2 *const region);
struct radv_sdma_surf radv_sdma_get_surf(const struct radv_device *const device, const struct radv_image *const image,
const VkImageSubresourceLayers subresource, const VkOffset3D offset,
const VkImageAspectFlags aspect_mask);
const VkImageSubresourceLayers subresource, const VkOffset3D offset);
void radv_sdma_copy_buffer_image(const struct radv_device *device, struct radeon_cmdbuf *cs,
const struct radv_sdma_surf *buf, const struct radv_sdma_surf *img,
const VkExtent3D extent, bool to_image);