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radeonsi: move PKT3_WRITE_DATA generation into a helper function

Browse source 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2019-01-17 15:07:03 -05:00
parent c252273f98
commit 4d5f8f39f3
6 changed files with 43 additions and 41 deletions
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25
src/gallium/drivers/radeonsi/si_cp_dma.c
View file

@ -581,3 +581,28 @@ void si_test_gds(struct si_context *sctx)
pipe_resource_reference(&dst, NULL);
exit(0);
}
void si_cp_write_data(struct si_context *sctx, struct r600_resource *buf,
unsigned offset, unsigned size, unsigned dst_sel,
unsigned engine, const void *data)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
assert(offset % 4 == 0);
assert(size % 4 == 0);
if (sctx->chip_class == SI && dst_sel == V_370_MEM)
dst_sel = V_370_MEM_GRBM;
radeon_add_to_buffer_list(sctx, cs, buf,
RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
uint64_t va = buf->gpu_address + offset;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + size/4, 0));
radeon_emit(cs, S_370_DST_SEL(dst_sel) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(engine));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit_array(cs, (const uint32_t*)data, size/4);
}

10
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -1821,7 +1821,6 @@ static void si_upload_bindless_descriptor(struct si_context *sctx,
unsigned num_dwords)
{
struct si_descriptors *desc = &sctx->bindless_descriptors;
struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned desc_slot_offset = desc_slot * 16;
uint32_t *data;
uint64_t va;
@ -1829,13 +1828,8 @@ static void si_upload_bindless_descriptor(struct si_context *sctx,
data = desc->list + desc_slot_offset;
va = desc->gpu_address + desc_slot_offset * 4;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + num_dwords, 0));
radeon_emit(cs, S_370_DST_SEL(V_370_TC_L2) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_ME));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit_array(cs, data, num_dwords);
si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address,
num_dwords * 4, V_370_TC_L2, V_370_ME, data);
}
static void si_upload_bindless_descriptors(struct si_context *sctx)

21
src/gallium/drivers/radeonsi/si_fence.c
View file

@ -259,21 +259,16 @@ static void si_fine_fence_set(struct si_context *ctx,
*fence_ptr = 0;
uint64_t fence_va = fine->buf->gpu_address + fine->offset;
radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
struct radeon_cmdbuf *cs = ctx->gfx_cs;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(ctx->chip_class >= CIK ? V_370_MEM
: V_370_MEM_GRBM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cs, fence_va);
radeon_emit(cs, fence_va >> 32);
radeon_emit(cs, 0x80000000);
uint32_t value = 0x80000000;
si_cp_write_data(ctx, fine->buf, fine->offset, 4,
V_370_MEM, V_370_PFP, &value);
} else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) {
uint64_t fence_va = fine->buf->gpu_address + fine->offset;
radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
si_cp_release_mem(ctx,
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,

13
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -526,17 +526,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
goto fail;
/* Initialize the memory. */
struct radeon_cmdbuf *cs = sctx->gfx_cs;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
: V_370_MEM_GRBM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_ME));
radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
radeon_emit(cs, sctx->wait_mem_number);
radeon_add_to_buffer_list(sctx, cs, sctx->wait_mem_scratch,
RADEON_USAGE_WRITE, RADEON_PRIO_FENCE);
si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
V_370_MEM, V_370_ME, &sctx->wait_mem_number);
}
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads

3
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1176,6 +1176,9 @@ void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf
uint64_t offset, unsigned size);
void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
void si_test_gds(struct si_context *sctx);
void si_cp_write_data(struct si_context *sctx, struct r600_resource *buf,
unsigned offset, unsigned size, unsigned dst_sel,
unsigned engine, const void *data);
/* si_debug.c */
void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,

12
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -1592,17 +1592,11 @@ si_draw_rectangle(struct blitter_context *blitter,
void si_trace_emit(struct si_context *sctx)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
: V_370_MEM_GRBM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_ME));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, trace_id);
si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
0, 4, V_370_MEM, V_370_ME, &trace_id);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));