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aco: implement 16-bit nir_op_f2i64/nir_op_f2u64

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4509>
This commit is contained in:
Samuel Pitoiset 2020-04-10 15:21:52 +02:00 • committed by Marge Bot
parent 729bdc0d70
commit 4cfaef68d7
1 changed files with 10 additions and 4 deletions
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14
src/amd/compiler/aco_instruction_selection.cpp
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@ -2351,7 +2351,10 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
case nir_op_f2i64: {
Temp src = get_alu_src(ctx, instr->src[0]);
if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
if (instr->src[0].src.ssa->bit_size == 16)
src = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src);
if (instr->src[0].src.ssa->bit_size <= 32 && dst.type() == RegType::vgpr) {
Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
@ -2377,7 +2380,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
} else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
} else if (instr->src[0].src.ssa->bit_size <= 32 && dst.type() == RegType::sgpr) {
if (src.type() == RegType::vgpr)
src = bld.as_uniform(src);
Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
@ -2427,7 +2430,10 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
case nir_op_f2u64: {
Temp src = get_alu_src(ctx, instr->src[0]);
if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
if (instr->src[0].src.ssa->bit_size == 16)
src = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src);
if (instr->src[0].src.ssa->bit_size <= 32 && dst.type() == RegType::vgpr) {
Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
@ -2450,7 +2456,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
} else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
} else if (instr->src[0].src.ssa->bit_size <= 32 && dst.type() == RegType::sgpr) {
if (src.type() == RegType::vgpr)
src = bld.as_uniform(src);
Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));