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ac/gpu_info: rename num_tcc_blocks -> max_tcc_blocks

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Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8892>
This commit is contained in:
Marek Olšák 2021-02-04 00:50:32 -05:00 • committed by Marge Bot
parent 7099513380
commit 4ccf664f05
4 changed files with 11 additions and 11 deletions
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6
src/amd/common/ac_gpu_info.c
View file

@ -640,7 +640,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
/* convert the shader/memory clocks from KHz to MHz */
info->max_shader_clock = amdinfo->max_engine_clk / 1000;
info->max_memory_clock = amdinfo->max_memory_clk / 1000;
info->num_tcc_blocks = device_info.num_tcc_blocks;
info->max_tcc_blocks = device_info.num_tcc_blocks;
info->max_se = amdinfo->num_shader_engines;
info->max_sa_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode = (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
@ -704,7 +704,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->tcc_harvested = device_info.tcc_disabled_mask != 0;
} else {
/* This is a hack, but it's all we can do without a kernel upgrade. */
info->tcc_harvested = (info->vram_size / info->num_tcc_blocks) != 512 * 1024 * 1024;
info->tcc_harvested = (info->vram_size / info->max_tcc_blocks) != 512 * 1024 * 1024;
}
} else {
info->tcc_cache_line_size = 64;
@ -1061,7 +1061,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " all_vram_visible = %u\n", info->all_vram_visible);
fprintf(f, " smart_access_memory = %u\n", info->smart_access_memory);
fprintf(f, " num_sdp_interfaces = %u\n", info->num_sdp_interfaces);
fprintf(f, " num_tcc_blocks = %i\n", info->num_tcc_blocks);
fprintf(f, " max_tcc_blocks = %i\n", info->max_tcc_blocks);
fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
fprintf(f, " tcc_harvested = %u\n", info->tcc_harvested);
fprintf(f, " pc_lines = %u\n", info->pc_lines);

2
src/amd/common/ac_gpu_info.h
View file

@ -105,7 +105,7 @@ struct radeon_info {
bool has_l2_uncached;
bool r600_has_virtual_memory;
uint32_t num_sdp_interfaces;
uint32_t num_tcc_blocks;
uint32_t max_tcc_blocks;
uint32_t tcc_cache_line_size;
bool tcc_harvested;
unsigned pc_lines;

2
src/gallium/drivers/radeonsi/si_perfcounter.c
View file

@ -1504,7 +1504,7 @@ void si_init_perfcounters(struct si_screen *screen)
!strcmp(block->b->b->name, "RMI"))
block->num_instances = screen->info.max_se;
else if (!strcmp(block->b->b->name, "TCC"))
block->num_instances = screen->info.num_tcc_blocks;
block->num_instances = screen->info.max_tcc_blocks;
else if (!strcmp(block->b->b->name, "IA"))
block->num_instances = MAX2(1, screen->info.max_se / 2);
else if (!strcmp(block->b->b->name, "TA") ||

12
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

@ -491,25 +491,25 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
switch (ws->info.family) {
case CHIP_HAINAN:
case CHIP_KABINI:
ws->info.num_tcc_blocks = 2;
ws->info.max_tcc_blocks = 2;
break;
case CHIP_VERDE:
case CHIP_OLAND:
case CHIP_BONAIRE:
case CHIP_KAVERI:
ws->info.num_tcc_blocks = 4;
ws->info.max_tcc_blocks = 4;
break;
case CHIP_PITCAIRN:
ws->info.num_tcc_blocks = 8;
ws->info.max_tcc_blocks = 8;
break;
case CHIP_TAHITI:
ws->info.num_tcc_blocks = 12;
ws->info.max_tcc_blocks = 12;
break;
case CHIP_HAWAII:
ws->info.num_tcc_blocks = 16;
ws->info.max_tcc_blocks = 16;
break;
default:
ws->info.num_tcc_blocks = 0;
ws->info.max_tcc_blocks = 0;
break;
}