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radv: move all NIR pass outside of ACO
This has several advantages: - it generates roughly the same NIR for both compiler backends (this might help for debugging purposes) - it might allow to move around some NIR pass to improve compile time - it might help for RadeonSI support - it improves fossils-db stats for RADV/LLVM (this shouldn't matter much but it's a win for free) fossil-db (Navi/LLVM): Totals from 80732 (59.18% of 136420) affected shaders: SGPRs: 5390036 -> 5382843 (-0.13%); split: -3.38%, +3.24% VGPRs: 3910932 -> 3890320 (-0.53%); split: -2.38%, +1.85% SpillSGPRs: 319212 -> 283149 (-11.30%); split: -17.69%, +6.39% SpillVGPRs: 14668 -> 14324 (-2.35%); split: -7.53%, +5.18% CodeSize: 265360860 -> 267572132 (+0.83%); split: -0.47%, +1.30% Scratch: 5338112 -> 6134784 (+14.92%); split: -2.65%, +17.57% MaxWaves: 1077230 -> 1086902 (+0.90%); split: +2.79%, -1.90% No fossils-db changes on RADV/ACO. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7077>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
9aa89b36fc
commit
4ca1030774
2 changed files with 145 additions and 139 deletions
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@ -377,49 +377,6 @@ RegClass get_reg_class(isel_context *ctx, RegType type, unsigned components, uns
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return RegClass::get(type, components * bitsize / 8u);
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}
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bool
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mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
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unsigned bit_size,
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unsigned num_components,
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nir_intrinsic_instr *low, nir_intrinsic_instr *high)
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{
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if (num_components > 4)
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return false;
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/* >128 bit loads are split except with SMEM */
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if (bit_size * num_components > 128)
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return false;
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uint32_t align;
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if (align_offset)
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align = 1 << (ffs(align_offset) - 1);
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else
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align = align_mul;
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switch (low->intrinsic) {
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case nir_intrinsic_load_global:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_push_constant:
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return align % (bit_size == 8 ? 2 : 4) == 0;
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case nir_intrinsic_load_deref:
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case nir_intrinsic_store_deref:
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assert(nir_src_as_deref(low->src[0])->mode == nir_var_mem_shared);
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/* fallthrough */
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case nir_intrinsic_load_shared:
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case nir_intrinsic_store_shared:
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if (bit_size * num_components > 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
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return align % 16 == 0;
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else
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return align % (bit_size == 8 ? 2 : 4) == 0;
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default:
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return false;
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}
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return false;
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}
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void
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setup_vs_output_info(isel_context *ctx, nir_shader *nir,
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bool export_prim_id, bool export_clip_dists,
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@ -633,108 +590,12 @@ setup_variables(isel_context *ctx, nir_shader *nir)
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}
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}
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unsigned
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lower_bit_size_callback(const nir_alu_instr *alu, void *_)
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{
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if (nir_op_is_vec(alu->op))
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return 0;
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unsigned bit_size = alu->dest.dest.ssa.bit_size;
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if (nir_alu_instr_is_comparison(alu))
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bit_size = nir_src_bit_size(alu->src[0].src);
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if (bit_size >= 32 || bit_size == 1)
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return 0;
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if (alu->op == nir_op_bcsel)
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return 0;
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const nir_op_info *info = &nir_op_infos[alu->op];
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if (info->is_conversion)
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return 0;
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bool is_integer = info->output_type & (nir_type_uint | nir_type_int);
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for (unsigned i = 0; is_integer && (i < info->num_inputs); i++)
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is_integer = info->input_types[i] & (nir_type_uint | nir_type_int);
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return is_integer ? 32 : 0;
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}
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void
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setup_nir(isel_context *ctx, nir_shader *nir)
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{
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/* the variable setup has to be done before lower_io / CSE */
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setup_variables(ctx, nir);
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bool lower_to_scalar = false;
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bool lower_pack = false;
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nir_variable_mode robust_modes = (nir_variable_mode)0;
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if (ctx->options->robust_buffer_access) {
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robust_modes = nir_var_mem_ubo |
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nir_var_mem_ssbo |
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nir_var_mem_global |
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nir_var_mem_push_const;
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}
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if (nir_opt_load_store_vectorize(nir,
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nir_var_mem_ssbo | nir_var_mem_ubo |
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nir_var_mem_push_const | nir_var_mem_shared |
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nir_var_mem_global,
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mem_vectorize_callback, robust_modes)) {
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lower_to_scalar = true;
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lower_pack = true;
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}
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lower_to_scalar |= nir_opt_shrink_vectors(nir);
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if (lower_to_scalar)
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nir_lower_alu_to_scalar(nir, NULL, NULL);
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if (lower_pack)
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nir_lower_pack(nir);
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/* lower ALU operations */
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nir_lower_int64(nir);
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if (nir_lower_bit_size(nir, lower_bit_size_callback, NULL))
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nir_copy_prop(nir); /* allow nir_opt_idiv_const() to optimize lowered divisions */
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nir_opt_idiv_const(nir, 32);
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nir_lower_idiv(nir, nir_lower_idiv_precise);
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/* optimize the lowered ALU operations */
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bool more_algebraic = true;
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while (more_algebraic) {
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more_algebraic = false;
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NIR_PASS_V(nir, nir_copy_prop);
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NIR_PASS_V(nir, nir_opt_dce);
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NIR_PASS_V(nir, nir_opt_constant_folding);
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NIR_PASS(more_algebraic, nir, nir_opt_algebraic);
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}
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/* Do late algebraic optimization to turn add(a, neg(b)) back into
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* subs, then the mandatory cleanup after algebraic. Note that it may
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* produce fnegs, and if so then we need to keep running to squash
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* fneg(fneg(a)).
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*/
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bool more_late_algebraic = true;
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while (more_late_algebraic) {
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more_late_algebraic = false;
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NIR_PASS(more_late_algebraic, nir, nir_opt_algebraic_late);
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NIR_PASS_V(nir, nir_opt_constant_folding);
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NIR_PASS_V(nir, nir_copy_prop);
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NIR_PASS_V(nir, nir_opt_dce);
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NIR_PASS_V(nir, nir_opt_cse);
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}
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/* cleanup passes */
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nir_lower_load_const_to_scalar(nir);
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nir_move_options move_opts = (nir_move_options)(
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nir_move_const_undef | nir_move_load_ubo | nir_move_load_input |
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nir_move_comparisons | nir_move_copies);
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nir_opt_sink(nir, move_opts);
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nir_opt_move(nir, move_opts);
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nir_convert_to_lcssa(nir, true, false);
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nir_lower_phis_to_scalar(nir);
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@ -2902,6 +2902,77 @@ void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
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(cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
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}
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static bool
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mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
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unsigned bit_size,
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unsigned num_components,
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nir_intrinsic_instr *low, nir_intrinsic_instr *high)
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{
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if (num_components > 4)
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return false;
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/* >128 bit loads are split except with SMEM */
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if (bit_size * num_components > 128)
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return false;
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uint32_t align;
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if (align_offset)
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align = 1 << (ffs(align_offset) - 1);
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else
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align = align_mul;
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switch (low->intrinsic) {
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case nir_intrinsic_load_global:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_push_constant:
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return align % (bit_size == 8 ? 2 : 4) == 0;
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case nir_intrinsic_load_deref:
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case nir_intrinsic_store_deref:
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assert(nir_src_as_deref(low->src[0])->mode == nir_var_mem_shared);
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/* fallthrough */
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case nir_intrinsic_load_shared:
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case nir_intrinsic_store_shared:
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if (bit_size * num_components > 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
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return align % 16 == 0;
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else
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return align % (bit_size == 8 ? 2 : 4) == 0;
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default:
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return false;
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}
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return false;
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}
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static unsigned
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lower_bit_size_callback(const nir_alu_instr *alu, void *_)
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{
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if (nir_op_is_vec(alu->op))
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return 0;
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unsigned bit_size = alu->dest.dest.ssa.bit_size;
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if (nir_alu_instr_is_comparison(alu))
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bit_size = nir_src_bit_size(alu->src[0].src);
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if (bit_size >= 32 || bit_size == 1)
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return 0;
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if (alu->op == nir_op_bcsel)
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return 0;
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const nir_op_info *info = &nir_op_infos[alu->op];
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if (info->is_conversion)
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return 0;
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bool is_integer = info->output_type & (nir_type_uint | nir_type_int);
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for (unsigned i = 0; is_integer && (i < info->num_inputs); i++)
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is_integer = info->input_types[i] & (nir_type_uint | nir_type_int);
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return is_integer ? 32 : 0;
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}
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VkResult radv_create_shaders(struct radv_pipeline *pipeline,
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struct radv_device *device,
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struct radv_pipeline_cache *cache,
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@ -3029,6 +3100,80 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
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NIR_PASS_V(nir[i], nir_lower_memory_model);
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radv_lower_io(device, nir[i]);
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bool lower_to_scalar = false;
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bool lower_pack = false;
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nir_variable_mode robust_modes = (nir_variable_mode)0;
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if (device->robust_buffer_access) {
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robust_modes = nir_var_mem_ubo |
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nir_var_mem_ssbo |
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nir_var_mem_global |
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nir_var_mem_push_const;
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}
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if (nir_opt_load_store_vectorize(nir[i],
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nir_var_mem_ssbo | nir_var_mem_ubo |
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nir_var_mem_push_const | nir_var_mem_shared |
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nir_var_mem_global,
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mem_vectorize_callback, robust_modes)) {
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lower_to_scalar = true;
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lower_pack = true;
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}
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lower_to_scalar |= nir_opt_shrink_vectors(nir[i]);
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if (lower_to_scalar)
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nir_lower_alu_to_scalar(nir[i], NULL, NULL);
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if (lower_pack)
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nir_lower_pack(nir[i]);
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/* lower ALU operations */
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/* TODO: Some 64-bit tests crash inside LLVM. */
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if (!radv_use_llvm_for_stage(device, i))
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nir_lower_int64(nir[i]);
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if (nir_lower_bit_size(nir[i], lower_bit_size_callback, NULL))
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nir_copy_prop(nir[i]); /* allow nir_opt_idiv_const() to optimize lowered divisions */
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/* TODO: Implement nir_op_uadd_sat with LLVM. */
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if (!radv_use_llvm_for_stage(device, i))
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nir_opt_idiv_const(nir[i], 32);
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nir_lower_idiv(nir[i], nir_lower_idiv_precise);
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/* optimize the lowered ALU operations */
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bool more_algebraic = true;
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while (more_algebraic) {
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more_algebraic = false;
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NIR_PASS_V(nir[i], nir_copy_prop);
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NIR_PASS_V(nir[i], nir_opt_dce);
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NIR_PASS_V(nir[i], nir_opt_constant_folding);
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NIR_PASS(more_algebraic, nir[i], nir_opt_algebraic);
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}
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/* Do late algebraic optimization to turn add(a,
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* neg(b)) back into subs, then the mandatory cleanup
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* after algebraic. Note that it may produce fnegs,
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* and if so then we need to keep running to squash
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* fneg(fneg(a)).
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*/
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bool more_late_algebraic = true;
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while (more_late_algebraic) {
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more_late_algebraic = false;
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NIR_PASS(more_late_algebraic, nir[i], nir_opt_algebraic_late);
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NIR_PASS_V(nir[i], nir_opt_constant_folding);
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NIR_PASS_V(nir[i], nir_copy_prop);
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NIR_PASS_V(nir[i], nir_opt_dce);
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NIR_PASS_V(nir[i], nir_opt_cse);
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}
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/* cleanup passes */
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nir_lower_load_const_to_scalar(nir[i]);
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nir_move_options move_opts = (nir_move_options)(
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nir_move_const_undef | nir_move_load_ubo | nir_move_load_input |
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nir_move_comparisons | nir_move_copies);
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nir_opt_sink(nir[i], move_opts);
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nir_opt_move(nir[i], move_opts);
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}
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}
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