From 4c92084ed970bc8f75ebd1dbeca5fa1b387bebe7 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 28 Feb 2024 12:22:31 -0800 Subject: [PATCH] anv/trtt: invalidate the TLB after writing TR-TT entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We're changing the memory address translation tables, we should invalidate their cache. It seems i915.ko is already doing this for us in between batches. The xe.ko driver only adds invalidates to the ring before submissions if scratch page is enabled in the VM (which it is today, but may change in the future), and after some vm_bind and all vm_unbind ioctls, but we don't use vm_bind for TR-TT. Still, it won't hurt to have it here righ tnow. v2: Use PIPE_CONTROL_length (José). Reviewed-by: Lionel Landwerlin (v1) Reviewed-by: José Roberto de Souza Signed-off-by: Paulo Zanoni Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 981e38f736d..fa33953f9a2 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -5972,8 +5972,12 @@ VkResult genX(write_trtt_entries)(struct anv_trtt_submission *submit) { #if GFX_VER >= 12 + const struct intel_device_info *devinfo = + submit->sparse->queue->device->info; + size_t batch_size = submit->l3l2_binds_len * 20 + - submit->l1_binds_len * 16 + 8; + submit->l1_binds_len * 16 + + GENX(PIPE_CONTROL_length) * sizeof(uint32_t) + 8; STACK_ARRAY(uint32_t, cmds, batch_size); struct anv_batch batch = { .start = cmds, @@ -6066,6 +6070,10 @@ genX(write_trtt_entries)(struct anv_trtt_submission *submit) i += extra_writes; } + genx_batch_emit_pipe_control(&batch, devinfo, _3D, + ANV_PIPE_CS_STALL_BIT | + ANV_PIPE_TLB_INVALIDATE_BIT); + anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe); assert(batch.next <= batch.end);