From 4c67924251292106963afa4f27639fe5d3c32eef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Iv=C3=A1n=20Briano?= Date: Wed, 16 Jun 2021 15:49:25 -0700 Subject: [PATCH] intel/nir: Fix txs for null surfaces Closes: #4860 Fixes: 05a37e24220 ("intel/nir: Set lower txs with non-zero LOD") Reviewed-by: Lionel Landwerlin Part-of: --- src/compiler/nir/nir_lower_tex.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index e96676c2ffa..cf8275c5786 100644 --- a/src/compiler/nir/nir_lower_tex.c +++ b/src/compiler/nir/nir_lower_tex.c @@ -1127,10 +1127,14 @@ nir_lower_txs_lod(nir_builder *b, nir_tex_instr *tex) nir_instr_rewrite_src(&tex->instr, &tex->src[lod_idx].src, nir_src_for_ssa(nir_imm_int(b, 0))); - /* TXS(LOD) = max(TXS(0) >> LOD, 1) */ + /* TXS(LOD) = max(TXS(0) >> LOD, 1) + * But we do min(TXS(0), TXS(LOD)) to catch the case of a null surface, + * which should return 0, not 1. + */ b->cursor = nir_after_instr(&tex->instr); - nir_ssa_def *minified = nir_imax(b, nir_ushr(b, &tex->dest.ssa, lod), - nir_imm_int(b, 1)); + nir_ssa_def *minified = nir_imin(b, &tex->dest.ssa, + nir_imax(b, nir_ushr(b, &tex->dest.ssa, lod), + nir_imm_int(b, 1))); /* Make sure the component encoding the array size (if any) is not * minified.