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radv: remove remaining unused pCreateInfo pointers

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16958>
This commit is contained in:
Samuel Pitoiset 2022-06-01 16:25:59 +02:00 • committed by Marge Bot
parent 653ded5704
commit 4bd6519b6b
1 changed files with 16 additions and 32 deletions
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48
src/amd/vulkan/radv_pipeline.c
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@ -973,7 +973,6 @@ radv_pipeline_has_dynamic_ds_states(const struct radv_graphics_pipeline *pipelin
static bool
radv_pipeline_out_of_order_rast(struct radv_graphics_pipeline *pipeline,
const struct radv_blend_state *blend,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
unsigned colormask = blend->cb_target_enabled_4bit;
@ -1068,7 +1067,6 @@ radv_pipeline_out_of_order_rast(struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline,
const struct radv_blend_state *blend,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
@ -1111,7 +1109,7 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline,
/* Determine if the driver can enable out-of-order
* rasterization internally.
*/
out_of_order_rast = radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo, info);
out_of_order_rast = radv_pipeline_out_of_order_rast(pipeline, blend, info);
}
ms->pa_sc_aa_config = 0;
@ -1175,7 +1173,6 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline,
static void
gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
@ -1350,7 +1347,6 @@ radv_pipeline_is_blend_enabled(const struct radv_graphics_pipeline *pipeline,
static uint64_t
radv_pipeline_needed_dynamic_state(const struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
bool has_color_att = radv_pipeline_has_color_attachments(&info->ri);
@ -1969,7 +1965,6 @@ radv_pipeline_init_graphics_info(struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_input_assembly_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
struct radv_shader *tes = pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
@ -1991,10 +1986,9 @@ radv_pipeline_init_input_assembly_state(struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
uint64_t needed_states = radv_pipeline_needed_dynamic_state(pipeline, pCreateInfo, info);
uint64_t needed_states = radv_pipeline_needed_dynamic_state(pipeline, info);
uint64_t states = needed_states;
pipeline->dynamic_state = default_dynamic_state;
@ -2180,7 +2174,6 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_raster_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
@ -2216,7 +2209,6 @@ radv_pipeline_init_raster_state(struct radv_graphics_pipeline *pipeline,
static struct radv_depth_stencil_state
radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
@ -5132,7 +5124,6 @@ struct radv_bin_size_entry {
static VkExtent2D
radv_gfx9_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
@ -5397,7 +5388,6 @@ radv_gfx9_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
static VkExtent2D
radv_gfx10_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
@ -5483,7 +5473,6 @@ radv_gfx10_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_disabled_binning_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
@ -5544,7 +5533,6 @@ radv_get_binning_settings(const struct radv_physical_device *pdev)
static void
radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_blend_state *blend,
const struct radv_graphics_pipeline_info *info)
{
@ -5555,9 +5543,9 @@ radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
VkExtent2D bin_size;
if (device->physical_device->rad_info.gfx_level >= GFX10) {
bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo, info);
bin_size = radv_gfx10_compute_bin_size(pipeline, info);
} else if (device->physical_device->rad_info.gfx_level == GFX9) {
bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo, info);
bin_size = radv_gfx9_compute_bin_size(pipeline, info);
} else
unreachable("Unhandled generation for binning bin size calculation");
@ -5576,7 +5564,7 @@ radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
} else
radv_pipeline_init_disabled_binning_state(pipeline, pCreateInfo, info);
radv_pipeline_init_disabled_binning_state(pipeline, info);
}
static void
@ -6786,7 +6774,6 @@ radv_pipeline_emit_pm4(struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_vertex_input_state(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_info *info)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
@ -6885,8 +6872,7 @@ radv_pipeline_init_shader_stages_state(struct radv_graphics_pipeline *pipeline)
static uint32_t
radv_pipeline_init_vgt_gs_out(struct radv_graphics_pipeline *pipeline,
const struct radv_graphics_pipeline_info *info,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
const struct radv_graphics_pipeline_info *info)
{
uint32_t gs_out;
@ -6912,7 +6898,6 @@ radv_pipeline_init_vgt_gs_out(struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_create_info *extra,
struct radv_blend_state *blend_state,
struct radv_depth_stencil_state *ds_state,
@ -7010,21 +6995,21 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
return result;
pipeline->spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo, &info);
radv_pipeline_init_multisample_state(pipeline, &blend, &info);
if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, &info);
radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, &info);
radv_pipeline_init_input_assembly_state(pipeline, &info);
radv_pipeline_init_dynamic_state(pipeline, &info);
pipeline->negative_one_to_one = info.vp.negative_one_to_one;
radv_pipeline_init_raster_state(pipeline, pCreateInfo, &info);
radv_pipeline_init_raster_state(pipeline, &info);
struct radv_depth_stencil_state ds_state =
radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, &info);
radv_pipeline_init_depth_stencil_state(pipeline, &info);
if (device->physical_device->rad_info.gfx_level >= GFX10_3)
gfx103_pipeline_init_vrs_state(pipeline, pCreateInfo, &info);
gfx103_pipeline_init_vrs_state(pipeline, &info);
/* Ensure that some export memory is always allocated, for two reasons:
*
@ -7062,11 +7047,11 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
}
if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
radv_pipeline_init_vertex_input_state(pipeline, pCreateInfo, &info);
radv_pipeline_init_vertex_input_state(pipeline, &info);
uint32_t vgt_gs_out_prim_type = radv_pipeline_init_vgt_gs_out(pipeline, &info, pCreateInfo);
uint32_t vgt_gs_out_prim_type = radv_pipeline_init_vgt_gs_out(pipeline, &info);
radv_pipeline_init_binning_state(pipeline, pCreateInfo, &blend, &info);
radv_pipeline_init_binning_state(pipeline, &blend, &info);
radv_pipeline_init_shader_stages_state(pipeline);
radv_pipeline_init_scratch(device, &pipeline->base);
@ -7084,8 +7069,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
pipeline->base.dynamic_offset_count = pipeline_layout->dynamic_offset_count;
if (extra) {
radv_pipeline_init_extra(pipeline, pCreateInfo, extra, &blend, &ds_state, &info,
&vgt_gs_out_prim_type);
radv_pipeline_init_extra(pipeline, extra, &blend, &ds_state, &info, &vgt_gs_out_prim_type);
}
radv_pipeline_emit_pm4(pipeline, &blend, &ds_state, vgt_gs_out_prim_type, &info);