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radv: enable TC-compat HTILE in GENERAL on GFX10+

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GFX10+ supports compressed writes to HTILE, so it should just work
to skip decompressions when transitioning from/to GENERAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>
This commit is contained in:
Samuel Pitoiset 2020-12-10 18:29:03 +01:00 • committed by Marge Bot
parent 326c7312bf
commit 4bb92d9145
4 changed files with 24 additions and 15 deletions
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16
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1763,7 +1763,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
!radv_image_is_tc_compat_htile(image)) !radv_image_is_tc_compat_htile(image))
return; return;
if (!radv_layout_is_htile_compressed(image, layout, in_render_loop, if (!radv_layout_is_htile_compressed(cmd_buffer->device, image, layout, in_render_loop,
radv_image_queue_family_mask(image, radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index, cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index))) { cmd_buffer->queue_family_index))) {
@ -1806,7 +1806,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
uint32_t db_z_info = ds->db_z_info; uint32_t db_z_info = ds->db_z_info;
uint32_t db_stencil_info = ds->db_stencil_info; uint32_t db_stencil_info = ds->db_stencil_info;
if (!radv_layout_is_htile_compressed(image, layout, in_render_loop, if (!radv_layout_is_htile_compressed(cmd_buffer->device, image, layout, in_render_loop,
radv_image_queue_family_mask(image, radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index, cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index))) { cmd_buffer->queue_family_index))) {
@ -2419,7 +2419,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale; cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
} }
if (radv_layout_is_htile_compressed(iview->image, layout, in_render_loop, if (radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop,
radv_image_queue_family_mask(iview->image, radv_image_queue_family_mask(iview->image,
cmd_buffer->queue_family_index, cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index))) { cmd_buffer->queue_family_index))) {
@ -6048,16 +6048,18 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
const VkImageSubresourceRange *range, const VkImageSubresourceRange *range,
struct radv_sample_locations_state *sample_locs) struct radv_sample_locations_state *sample_locs)
{ {
struct radv_device *device = cmd_buffer->device;
if (!radv_image_has_htile(image)) if (!radv_image_has_htile(image))
return; return;
if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
radv_initialize_htile(cmd_buffer, image, range); radv_initialize_htile(cmd_buffer, image, range);
} else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) && } else if (!radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop, src_queue_mask) &&
radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) { radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
radv_initialize_htile(cmd_buffer, image, range); radv_initialize_htile(cmd_buffer, image, range);
} else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) && } else if (radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop, src_queue_mask) &&
!radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) { !radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;

16
src/amd/vulkan/radv_image.c
View file

@ -1744,7 +1744,8 @@ radv_image_view_init(struct radv_image_view *iview,
} }
} }
bool radv_layout_is_htile_compressed(const struct radv_image *image, bool radv_layout_is_htile_compressed(const struct radv_device *device,
const struct radv_image *image,
VkImageLayout layout, VkImageLayout layout,
bool in_render_loop, bool in_render_loop,
unsigned queue_mask) unsigned queue_mask)
@ -1765,10 +1766,15 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image,
* depth pass because this allows compression and this reduces * depth pass because this allows compression and this reduces
* the number of decompressions from/to GENERAL. * the number of decompressions from/to GENERAL.
*/ */
return radv_image_is_tc_compat_htile(image) && if (radv_image_is_tc_compat_htile(image) &&
queue_mask == (1u << RADV_QUEUE_GENERAL) && queue_mask == (1u << RADV_QUEUE_GENERAL)) {
!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT) && /* GFX10+ supports compressed writes to HTILE. */
!in_render_loop; return device->physical_device->rad_info.chip_class >= GFX10 ||
(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
!in_render_loop);
} else {
return false;
}
default: default:
return radv_image_is_tc_compat_htile(image); return radv_image_is_tc_compat_htile(image);
} }

4
src/amd/vulkan/radv_meta_clear.c
View file

@ -703,7 +703,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
iview->base_mip == 0 && iview->base_mip == 0 &&
iview->base_layer == 0 && iview->base_layer == 0 &&
iview->layer_count == iview->image->info.array_size && iview->layer_count == iview->image->info.array_size &&
radv_layout_is_htile_compressed(iview->image, layout, in_render_loop, queue_mask) && radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop, queue_mask) &&
radv_image_extent_compare(iview->image, &iview->extent)) radv_image_extent_compare(iview->image, &iview->extent))
return true; return true;
return false; return false;
@ -1062,7 +1062,7 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview)) if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
return false; return false;
if (!radv_layout_is_htile_compressed(iview->image, image_layout, in_render_loop, if (!radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, image_layout, in_render_loop,
radv_image_queue_family_mask(iview->image, radv_image_queue_family_mask(iview->image,
cmd_buffer->queue_family_index, cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index))) cmd_buffer->queue_family_index)))

3
src/amd/vulkan/radv_private.h
View file

@ -1923,7 +1923,8 @@ struct radv_image {
* If this is false reads that don't use the htile should be able to return * If this is false reads that don't use the htile should be able to return
* correct results. * correct results.
*/ */
bool radv_layout_is_htile_compressed(const struct radv_image *image, bool radv_layout_is_htile_compressed(const struct radv_device *device,
const struct radv_image *image,
VkImageLayout layout, VkImageLayout layout,
bool in_render_loop, bool in_render_loop,
unsigned queue_mask); unsigned queue_mask);