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radv: only sync CP DMA for transfer operations or bottom pipe

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CP DMA can only be busy when the driver copies buffers. The
only affected Vulkan commands are vkCmdCopyBuffer() and
vkCmdUpdateBuffer() (because we fallback to a copy depending on
a threshold). Clear operations are currently not concerned
because the driver always syncs after the last DMA operation.

Per the spec, these two operations have to be externally
synchronized with VK_PIPELINE_STAGE_TRANSFER_BIT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2018-11-20 16:41:23 +01:00
parent 457ac6ce1e
commit 4b9bc4791b
1 changed files with 6 additions and 2 deletions
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8
src/amd/vulkan/radv_cmd_buffer.c
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@ -4496,7 +4496,9 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
/* Make sure CP DMA is idle because the driver might have performed a
* DMA operation for copying or filling buffers/images.
*/
si_cp_dma_wait_for_idle(cmd_buffer);
if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
si_cp_dma_wait_for_idle(cmd_buffer);
cmd_buffer->state.flush_bits |= dst_flush_bits;
}
@ -4553,7 +4555,9 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
/* Make sure CP DMA is idle because the driver might have performed a
* DMA operation for copying or filling buffers/images.
*/
si_cp_dma_wait_for_idle(cmd_buffer);
if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
si_cp_dma_wait_for_idle(cmd_buffer);
/* TODO: Emit EOS events for syncing PS/CS stages. */