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ac/nir/lower_ngg: add & use new scalar helpers for GS loads/stores
This simplifies the code and scalarizes the loads/stores. Scalar loads/stores will allow forwarding constant output components from stores to loads easily. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35352>
This commit is contained in:
Marek Olšák
Marge Bot
parent
f407129b7f
commit
4b6ae11207
3 changed files with 57 additions and 73 deletions
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@ -228,13 +228,18 @@ ac_nir_ngg_build_streamout_buffer_info(nir_builder *b,
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nir_def *buffer_offsets_ret[4],
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nir_def *emit_prim_ret[4]);
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unsigned
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ac_nir_get_lds_gs_out_slot_offset(ac_nir_prerast_out *pr_out, gl_varying_slot slot, unsigned component);
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unsigned
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ac_nir_ngg_get_xfb_lds_offset(ac_nir_prerast_out *pr_out, gl_varying_slot slot, unsigned component,
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bool data_is_16bit);
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void
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ac_nir_store_shared_gs_out(nir_builder *b, nir_def *value, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
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gl_varying_slot slot, unsigned component);
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nir_def *
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ac_nir_load_shared_gs_out(nir_builder *b, unsigned bit_size, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
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gl_varying_slot slot, unsigned component);
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void
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ac_nir_ngg_build_streamout_vertex(nir_builder *b, nir_xfb_info *info,
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unsigned stream, nir_def *so_buffer[4],
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@ -164,28 +164,14 @@ lower_ngg_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *intri
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*/
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u_foreach_bit64(slot, b->shader->info.outputs_written) {
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unsigned mask = gs_output_component_mask_with_stream(&s->out.infos[slot], stream);
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nir_def **output = s->out.outputs[slot];
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nir_def *undef = nir_undef(b, 1, 32);
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while (mask) {
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int start, count;
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u_bit_scan_consecutive_range(&mask, &start, &count);
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nir_def *values[4] = {0};
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for (int c = start; c < start + count; ++c) {
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if (!output[c]) {
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/* The shader hasn't written this output. */
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values[c - start] = undef;
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} else {
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assert(output[c]->bit_size == 32);
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values[c - start] = output[c];
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}
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}
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u_foreach_bit(c, mask) {
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/* The shader hasn't written this output yet. */
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if (!output[c])
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continue;
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nir_def *store_val = nir_vec(b, values, (unsigned)count);
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nir_store_shared(b, store_val, gs_emit_vtx_addr,
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.base = ac_nir_get_lds_gs_out_slot_offset(&s->out, slot, start),
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.align_mul = 4);
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ac_nir_store_shared_gs_out(b, output[c], gs_emit_vtx_addr, &s->out, slot, c);
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}
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/* Clear all outputs (they are undefined after emit_vertex) */
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@ -202,21 +188,16 @@ lower_ngg_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *intri
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nir_def **output_hi = s->out.outputs_16bit_hi[slot];
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nir_def *undef = nir_undef(b, 1, 16);
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while (mask) {
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int start, count;
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u_bit_scan_consecutive_range(&mask, &start, &count);
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nir_def *values[4] = {0};
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for (int c = start; c < start + count; ++c) {
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nir_def *lo = output_lo[c] ? output_lo[c] : undef;
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nir_def *hi = output_hi[c] ? output_hi[c] : undef;
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u_foreach_bit(c, mask) {
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/* The shader hasn't written this output yet. */
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if (!output_lo[c] && !output_hi[c])
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continue;
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values[c - start] = nir_pack_32_2x16_split(b, lo, hi);
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}
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nir_def *lo = output_lo[c] ? output_lo[c] : undef;
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nir_def *hi = output_hi[c] ? output_hi[c] : undef;
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nir_def *store_val = nir_pack_32_2x16_split(b, lo, hi);
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nir_def *store_val = nir_vec(b, values, (unsigned)count);
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nir_store_shared(b, store_val, gs_emit_vtx_addr,
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.base = ac_nir_get_lds_gs_out_slot_offset(&s->out, VARYING_SLOT_VAR0_16BIT + slot, start),
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.align_mul = 4);
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ac_nir_store_shared_gs_out(b, store_val, gs_emit_vtx_addr, &s->out, VARYING_SLOT_VAR0_16BIT + slot, c);
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}
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/* Clear all outputs (they are undefined after emit_vertex) */
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@ -383,16 +364,9 @@ ngg_gs_process_out_vertex(nir_builder *b, nir_def *out_vtx_lds_addr, lower_ngg_g
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u_foreach_bit64(slot, b->shader->info.outputs_written) {
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unsigned mask = gs_output_component_mask_with_stream(&s->out.infos[slot], 0);
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while (mask) {
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int start, count;
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u_bit_scan_consecutive_range(&mask, &start, &count);
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nir_def *load =
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nir_load_shared(b, count, 32, exported_out_vtx_lds_addr,
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.base = ac_nir_get_lds_gs_out_slot_offset(&s->out, slot, start),
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.align_mul = 4);
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for (int i = 0; i < count; i++)
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s->out.outputs[slot][start + i] = nir_channel(b, load, i);
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u_foreach_bit(c, mask) {
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s->out.outputs[slot][c] = ac_nir_load_shared_gs_out(b, 32, exported_out_vtx_lds_addr,
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&s->out, slot, c);
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}
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}
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@ -402,24 +376,15 @@ ngg_gs_process_out_vertex(nir_builder *b, nir_def *out_vtx_lds_addr, lower_ngg_g
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const unsigned mask_hi = gs_output_component_mask_with_stream(&s->out.infos_16bit_hi[i], 0);
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unsigned mask = mask_lo | mask_hi;
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while (mask) {
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int start, count;
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u_bit_scan_consecutive_range(&mask, &start, &count);
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nir_def *load =
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nir_load_shared(b, count, 32, exported_out_vtx_lds_addr,
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.base = ac_nir_get_lds_gs_out_slot_offset(&s->out, VARYING_SLOT_VAR0_16BIT + i, start),
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.align_mul = 4);
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u_foreach_bit(c, mask) {
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nir_def *load_val = ac_nir_load_shared_gs_out(b, 32, exported_out_vtx_lds_addr,
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&s->out, VARYING_SLOT_VAR0_16BIT + i, c);
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for (int j = 0; j < count; j++) {
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nir_def *val = nir_channel(b, load, j);
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unsigned comp = start + j;
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if (mask_lo & BITFIELD_BIT(c))
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s->out.outputs_16bit_lo[i][c] = nir_unpack_32_2x16_split_x(b, load_val);
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if (mask_lo & BITFIELD_BIT(comp))
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s->out.outputs_16bit_lo[i][comp] = nir_unpack_32_2x16_split_x(b, val);
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if (mask_hi & BITFIELD_BIT(comp))
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s->out.outputs_16bit_hi[i][comp] = nir_unpack_32_2x16_split_y(b, val);
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}
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if (mask_hi & BITFIELD_BIT(c))
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s->out.outputs_16bit_hi[i][c] = nir_unpack_32_2x16_split_y(b, load_val);
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}
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}
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@ -630,11 +595,8 @@ ngg_gs_cull_primitive(nir_builder *b, nir_def *tid_in_tg, nir_def *max_vtxcnt,
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for (unsigned i = 0; i < s->num_vertices_per_primitive; i++) {
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/* Load X, Y, W position components. Z is loaded only if we clip against POS. */
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for (unsigned c = 0; c < 4; c == 1 && !clip_against_pos ? c += 2 : c++) {
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pos[i][c] = nir_load_shared(b, 1, 32, vtxptr[i],
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.base = ac_nir_get_lds_gs_out_slot_offset(&s->out, VARYING_SLOT_POS, c),
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.align_mul = 4);
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}
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for (unsigned c = 0; c < 4; c == 1 && !clip_against_pos ? c += 2 : c++)
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pos[i][c] = ac_nir_load_shared_gs_out(b, 32, vtxptr[i], &s->out, VARYING_SLOT_POS, c);
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}
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nir_def *accepted_by_clipdist = nir_imm_true(b);
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@ -650,8 +612,8 @@ ngg_gs_cull_primitive(nir_builder *b, nir_def *tid_in_tg, nir_def *max_vtxcnt,
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if (!clip_against_pos) {
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for (unsigned i = 0; i < s->num_vertices_per_primitive; i++) {
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for (unsigned c = 0; c < 4; c++) {
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unsigned offset = ac_nir_get_lds_gs_out_slot_offset(&s->out, VARYING_SLOT_CLIP_VERTEX, c);
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clipvertex[i][c] = nir_load_shared(b, 1, 32, vtxptr[i], .base = offset, .align_mul = 4);
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clipvertex[i][c] = ac_nir_load_shared_gs_out(b, 32, vtxptr[i], &s->out,
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VARYING_SLOT_CLIP_VERTEX, c);
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}
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}
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}
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@ -668,10 +630,10 @@ ngg_gs_cull_primitive(nir_builder *b, nir_def *tid_in_tg, nir_def *max_vtxcnt,
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} else {
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/* Load clip distances. */
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u_foreach_bit(c, s->options->cull_clipdist_mask) {
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unsigned offset = ac_nir_get_lds_gs_out_slot_offset(&s->out, VARYING_SLOT_CLIP_DIST0 + c / 4, c % 4);
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for (unsigned i = 0; i < s->num_vertices_per_primitive; i++)
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clipdist[i][c] = nir_load_shared(b, 1, 32, vtxptr[i], .base = offset, .align_mul = 4);
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for (unsigned i = 0; i < s->num_vertices_per_primitive; i++) {
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clipdist[i][c] = ac_nir_load_shared_gs_out(b, 32, vtxptr[i], &s->out,
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VARYING_SLOT_CLIP_DIST0 + c / 4, c % 4);
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}
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}
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}
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@ -1310,7 +1310,7 @@ ac_nir_ngg_build_streamout_buffer_info(nir_builder *b,
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}
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}
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unsigned
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static unsigned
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ac_nir_get_lds_gs_out_slot_offset(ac_nir_prerast_out *pr_out, gl_varying_slot slot, unsigned component)
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{
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assert(component < 4);
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@ -1357,6 +1357,23 @@ ac_nir_ngg_get_xfb_lds_offset(ac_nir_prerast_out *pr_out, gl_varying_slot slot,
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return lds_slot_offset + util_bitcount(lds_component_mask & BITFIELD_MASK(component)) * 4;
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}
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void
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ac_nir_store_shared_gs_out(nir_builder *b, nir_def *value, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
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gl_varying_slot slot, unsigned component)
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{
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assert(value->num_components == 1);
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unsigned offset = ac_nir_get_lds_gs_out_slot_offset(pr_out, slot, component);
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nir_store_shared(b, value, vtxptr, .base = offset, .align_mul = 4);
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}
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nir_def *
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ac_nir_load_shared_gs_out(nir_builder *b, unsigned bit_size, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
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gl_varying_slot slot, unsigned component)
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{
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unsigned offset = ac_nir_get_lds_gs_out_slot_offset(pr_out, slot, component);
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return nir_load_shared(b, 1, bit_size, vtxptr, .base = offset, .align_mul = 4);
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}
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void
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ac_nir_ngg_build_streamout_vertex(nir_builder *b, nir_xfb_info *info,
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unsigned stream, nir_def *so_buffer[4],
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