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nvk: Replace more dev->pdev with nvk_device_physical()

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28105>
This commit is contained in:
Faith Ekstrand 2024-03-11 11:34:20 -05:00 • committed by Marge Bot
parent 9ddaa4ea10
commit 4b38ba5d70
11 changed files with 43 additions and 23 deletions
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3
src/nouveau/vulkan/nvk_buffer.c
View file

@ -157,6 +157,7 @@ nvk_GetDeviceBufferMemoryRequirements(
VkMemoryRequirements2 *pMemoryRequirements)
{
VK_FROM_HANDLE(nvk_device, dev, device);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
const uint32_t alignment =
nvk_get_buffer_alignment(nvk_device_physical(dev),
@ -166,7 +167,7 @@ nvk_GetDeviceBufferMemoryRequirements(
pMemoryRequirements->memoryRequirements = (VkMemoryRequirements) {
.size = align64(pInfo->pCreateInfo->size, alignment),
.alignment = alignment,
.memoryTypeBits = BITFIELD_MASK(dev->pdev->mem_type_count),
.memoryTypeBits = BITFIELD_MASK(pdev->mem_type_count),
};
vk_foreach_struct_const(ext, pMemoryRequirements->pNext) {

8
src/nouveau/vulkan/nvk_cmd_buffer.c
View file

@ -508,6 +508,9 @@ nvk_cmd_invalidate_deps(struct nvk_cmd_buffer *cmd,
uint32_t dep_count,
const VkDependencyInfo *deps)
{
struct nvk_device *dev = nvk_cmd_buffer_device(cmd);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
enum nvk_barrier barriers = 0;
for (uint32_t d = 0; d < dep_count; d++) {
@ -554,7 +557,7 @@ nvk_cmd_invalidate_deps(struct nvk_cmd_buffer *cmd,
if (barriers & (NVK_BARRIER_INVALIDATE_MME_DATA)) {
__push_immd(p, SUBC_NV9097, NV906F_SET_REFERENCE, 0);
if (nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d >= TURING_A)
if (pdev->info.cls_eng3d >= TURING_A)
P_IMMD(p, NVC597, MME_DMA_SYSMEMBAR, 0);
}
}
@ -843,6 +846,7 @@ void
nvk_cmd_buffer_dump(struct nvk_cmd_buffer *cmd, FILE *fp)
{
struct nvk_device *dev = nvk_cmd_buffer_device(cmd);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
util_dynarray_foreach(&cmd->pushes, struct nvk_cmd_push, p) {
if (p->map) {
@ -850,7 +854,7 @@ nvk_cmd_buffer_dump(struct nvk_cmd_buffer *cmd, FILE *fp)
.start = (uint32_t *)p->map,
.end = (uint32_t *)((char *)p->map + p->range),
};
vk_push_print(fp, &push, &dev->pdev->info);
vk_push_print(fp, &push, &pdev->info);
} else {
const uint64_t addr = p->addr;
fprintf(fp, "<%u B of INDIRECT DATA at 0x%" PRIx64 ">\n",

3
src/nouveau/vulkan/nvk_cmd_clear.c
View file

@ -291,6 +291,7 @@ nvk_CmdClearColorImage(VkCommandBuffer commandBuffer,
{
VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
struct nvk_device *dev = nvk_cmd_buffer_device(cmd);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
VK_FROM_HANDLE(nvk_image, image, _image);
VkClearValue clear_value = {
@ -304,7 +305,7 @@ nvk_CmdClearColorImage(VkCommandBuffer commandBuffer,
enum pipe_format p_format = vk_format_to_pipe_format(vk_format);
assert(p_format != PIPE_FORMAT_NONE);
if (!nil_format_supports_color_targets(&dev->pdev->info, p_format)) {
if (!nil_format_supports_color_targets(&pdev->info, p_format)) {
memset(&clear_value, 0, sizeof(clear_value));
util_format_pack_rgba(p_format, clear_value.color.uint32,
pColor->uint32, 1);

4
src/nouveau/vulkan/nvk_cmd_dispatch.c
View file

@ -75,7 +75,9 @@ nvk_push_dispatch_state_init(struct nvk_device *dev, struct nv_push *p)
static inline uint16_t
nvk_cmd_buffer_compute_cls(struct nvk_cmd_buffer *cmd)
{
return nvk_cmd_buffer_device(cmd)->pdev->info.cls_compute;
struct nvk_device *dev = nvk_cmd_buffer_device(cmd);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
return pdev->info.cls_compute;
}
void

4
src/nouveau/vulkan/nvk_cmd_draw.c
View file

@ -35,7 +35,9 @@
static inline uint16_t
nvk_cmd_buffer_3d_cls(struct nvk_cmd_buffer *cmd)
{
return nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d;
struct nvk_device *dev = nvk_cmd_buffer_device(cmd);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
return pdev->info.cls_eng3d;
}
void

7
src/nouveau/vulkan/nvk_device.c
View file

@ -58,6 +58,7 @@ nvk_slm_area_ensure(struct nvk_device *dev,
struct nvk_slm_area *area,
uint32_t bytes_per_thread)
{
struct nvk_physical_device *pdev = nvk_device_physical(dev);
assert(bytes_per_thread < (1 << 24));
/* TODO: Volta+doesn't use CRC */
@ -70,8 +71,8 @@ nvk_slm_area_ensure(struct nvk_device *dev,
*/
bytes_per_warp = align64(bytes_per_warp, 0x200);
uint64_t bytes_per_mp = bytes_per_warp * dev->pdev->info.max_warps_per_mp;
uint64_t bytes_per_tpc = bytes_per_mp * dev->pdev->info.mp_per_tpc;
uint64_t bytes_per_mp = bytes_per_warp * pdev->info.max_warps_per_mp;
uint64_t bytes_per_tpc = bytes_per_mp * pdev->info.mp_per_tpc;
/* The hardware seems to require this alignment for
* NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_LOWER.
@ -88,7 +89,7 @@ nvk_slm_area_ensure(struct nvk_device *dev,
if (likely(bytes_per_tpc <= area->bytes_per_tpc))
return VK_SUCCESS;
uint64_t size = bytes_per_tpc * dev->pdev->info.tpc_count;
uint64_t size = bytes_per_tpc * pdev->info.tpc_count;
/* The hardware seems to require this alignment for
* NV9097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER.

3
src/nouveau/vulkan/nvk_image.c
View file

@ -776,7 +776,8 @@ nvk_get_image_memory_requirements(struct nvk_device *dev,
VkImageAspectFlags aspects,
VkMemoryRequirements2 *pMemoryRequirements)
{
uint32_t memory_types = (1 << dev->pdev->mem_type_count) - 1;
struct nvk_physical_device *pdev = nvk_device_physical(dev);
uint32_t memory_types = (1 << pdev->mem_type_count) - 1;
// TODO hope for the best?

3
src/nouveau/vulkan/nvk_query_pool.c
View file

@ -1094,7 +1094,8 @@ nvk_cmd_copy_query_pool_results_mme(struct nvk_cmd_buffer *cmd,
VkQueryResultFlags flags)
{
/* TODO: vkCmdCopyQueryPoolResults() with a compute shader */
assert(nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d >= TURING_A);
ASSERTED struct nvk_device *dev = nvk_cmd_buffer_device(cmd);
assert(nvk_device_physical(dev)->info.cls_eng3d >= TURING_A);
struct nv_push *p = nvk_cmd_buffer_push(cmd, 13);
P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);

12
src/nouveau/vulkan/nvk_queue.c
View file

@ -47,17 +47,20 @@ static void
nvk_queue_state_dump_push(struct nvk_device *dev,
struct nvk_queue_state *qs, FILE *fp)
{
struct nvk_physical_device *pdev = nvk_device_physical(dev);
struct nv_push push = {
.start = (uint32_t *)qs->push.bo_map,
.end = (uint32_t *)qs->push.bo_map + qs->push.dw_count,
};
vk_push_print(fp, &push, &dev->pdev->info);
vk_push_print(fp, &push, &pdev->info);
}
VkResult
nvk_queue_state_update(struct nvk_device *dev,
struct nvk_queue_state *qs)
{
struct nvk_physical_device *pdev = nvk_device_physical(dev);
struct nouveau_ws_bo *bo;
uint32_t alloc_count, bytes_per_warp, bytes_per_tpc;
bool dirty = false;
@ -184,7 +187,7 @@ nvk_queue_state_update(struct nvk_device *dev,
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B(p, slm_per_tpc);
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C(p, 0xff);
if (dev->pdev->info.cls_compute < VOLTA_COMPUTE_A) {
if (pdev->info.cls_compute < VOLTA_COMPUTE_A) {
P_MTHD(p, NVA0C0, SET_SHADER_LOCAL_MEMORY_THROTTLED_A);
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A(p, slm_per_tpc >> 32);
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B(p, slm_per_tpc);
@ -203,7 +206,7 @@ nvk_queue_state_update(struct nvk_device *dev,
/* We set memory windows unconditionally. Otherwise, the memory window
* might be in a random place and cause us to fault off into nowhere.
*/
if (dev->pdev->info.cls_compute >= VOLTA_COMPUTE_A) {
if (pdev->info.cls_compute >= VOLTA_COMPUTE_A) {
uint64_t temp = 0xfeULL << 24;
P_MTHD(p, NVC3C0, SET_SHADER_SHARED_MEMORY_WINDOW_A);
P_NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A(p, temp >> 32);
@ -388,6 +391,7 @@ nvk_queue_submit_simple(struct nvk_queue *queue,
struct nouveau_ws_bo **extra_bos)
{
struct nvk_device *dev = nvk_queue_device(queue);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
struct nouveau_ws_bo *push_bo;
VkResult result;
@ -415,7 +419,7 @@ nvk_queue_submit_simple(struct nvk_queue *queue,
.start = (uint32_t *)dw,
.end = (uint32_t *)dw + dw_count,
};
vk_push_print(stderr, &push, &dev->pdev->info);
vk_push_print(stderr, &push, &pdev->info);
}
nouveau_ws_bo_unmap(push_bo, push_map);

5
src/nouveau/vulkan/nvk_sampler.c
View file

@ -291,6 +291,7 @@ nvk_CreateSampler(VkDevice device,
VkSampler *pSampler)
{
VK_FROM_HANDLE(nvk_device, dev, device);
struct nvk_physical_device *pdev = nvk_device_physical(dev);
struct nvk_sampler *sampler;
VkResult result;
@ -301,7 +302,7 @@ nvk_CreateSampler(VkDevice device,
uint32_t samp[8] = {};
sampler->plane_count = 1;
nvk_sampler_fill_header(dev->pdev, pCreateInfo, &sampler->vk, samp);
nvk_sampler_fill_header(pdev, pCreateInfo, &sampler->vk, samp);
result = nvk_descriptor_table_add(dev, &dev->samplers,
samp, sizeof(samp),
&sampler->planes[0].desc_index);
@ -332,7 +333,7 @@ nvk_CreateSampler(VkDevice device,
memset(samp, 0, sizeof(samp));
sampler->plane_count = 2;
nvk_sampler_fill_header(dev->pdev, &plane2_info, &sampler->vk, samp);
nvk_sampler_fill_header(pdev, &plane2_info, &sampler->vk, samp);
result = nvk_descriptor_table_add(dev, &dev->samplers,
samp, sizeof(samp),
&sampler->planes[1].desc_index);

14
src/nouveau/vulkan/nvk_shader.c
View file

@ -534,9 +534,11 @@ nvk_compile_nir(struct nvk_device *dev, nir_shader *nir,
VkResult
nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader)
{
struct nvk_physical_device *pdev = nvk_device_physical(dev);
uint32_t hdr_size = 0;
if (shader->info.stage != MESA_SHADER_COMPUTE) {
if (dev->pdev->info.cls_eng3d >= TURING_A)
if (pdev->info.cls_eng3d >= TURING_A)
hdr_size = TU102_SHADER_HEADER_SIZE;
else
hdr_size = GF100_SHADER_HEADER_SIZE;
@ -545,11 +547,11 @@ nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader)
/* Fermi needs 0x40 alignment
* Kepler+ needs the first instruction to be 0x80 aligned, so we waste 0x30 bytes
*/
int alignment = dev->pdev->info.cls_eng3d >= KEPLER_A ? 0x80 : 0x40;
int alignment = pdev->info.cls_eng3d >= KEPLER_A ? 0x80 : 0x40;
uint32_t total_size = 0;
if (dev->pdev->info.cls_eng3d >= KEPLER_A &&
dev->pdev->info.cls_eng3d < TURING_A &&
if (pdev->info.cls_eng3d >= KEPLER_A &&
pdev->info.cls_eng3d < TURING_A &&
hdr_size > 0) {
/* The instructions are what has to be aligned so we need to start at a
* small offset (0x30 B) into the upload area.
@ -566,7 +568,7 @@ nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader)
uint32_t data_offset = 0;
if (shader->data_size > 0) {
total_size = align(total_size, nvk_min_cbuf_alignment(&dev->pdev->info));
total_size = align(total_size, nvk_min_cbuf_alignment(&pdev->info));
data_offset = total_size;
total_size += shader->data_size;
}
@ -593,7 +595,7 @@ nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader)
shader->upload_size = total_size;
shader->hdr_addr = shader->upload_addr + hdr_offset;
if (dev->pdev->info.cls_eng3d < VOLTA_A) {
if (pdev->info.cls_eng3d < VOLTA_A) {
const uint64_t heap_base_addr =
nvk_heap_contiguous_base_address(&dev->shader_heap);
assert(shader->upload_addr - heap_base_addr < UINT32_MAX);