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i965: Rename intel_emit* to reflect their new location in brw_pipe_control

Browse source 
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Chris Wilson 2015-04-30 17:04:51 +01:00 • committed by Kenneth Graunke
parent 9d4b9f1e0c
commit 4b35ab9bdb
27 changed files with 55 additions and 55 deletions
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4
src/mesa/drivers/dri/i965/brw_blorp.cpp
View file

@ -220,7 +220,7 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
* data with different formats, which blorp does for stencil and depth
* data.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
@ -283,7 +283,7 @@ retry:
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,

4
src/mesa/drivers/dri/i965/brw_clear.c
View file

@ -184,7 +184,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* must be issued before the rectangle primitive used for the depth
* buffer clear operation.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
if (fb->MaxNumLayers > 0) {
for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
@ -204,7 +204,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
* followed by Depth FLUSH'
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}
/* Now, the HiZ buffer contains data that needs to be resolved to the depth

6
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -2003,9 +2003,9 @@ void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
drm_intel_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper);
void intel_batchbuffer_emit_mi_flush(struct brw_context *brw);
void intel_emit_post_sync_nonzero_flush(struct brw_context *brw);
void intel_emit_depth_stall_flushes(struct brw_context *brw);
void brw_emit_mi_flush(struct brw_context *brw);
void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
void brw_emit_depth_stall_flushes(struct brw_context *brw);
void gen7_emit_vs_workaround_flush(struct brw_context *brw);
void gen7_emit_cs_stall_flush(struct brw_context *brw);

4
src/mesa/drivers/dri/i965/brw_draw.c
View file

@ -217,7 +217,7 @@ static void brw_emit_prim(struct brw_context *brw,
* the besides the draw code.
*/
if (brw->always_flush_cache) {
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}
/* If indirect, emit a bunch of loads from the indirect BO. */
@ -284,7 +284,7 @@ static void brw_emit_prim(struct brw_context *brw,
ADVANCE_BATCH();
if (brw->always_flush_cache) {
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}
}

4
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
View file

@ -623,7 +623,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* write-flush must be issued before sending any DRAW commands on that
* render target.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
/* If we had to fall back to plain clear for any buffers, clear those now
* by calling into meta.
@ -677,7 +677,7 @@ brw_meta_resolve_color(struct brw_context *brw,
GLuint fbo, rbo;
struct rect rect;
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
_mesa_meta_begin(ctx, MESA_META_ALL);

8
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
View file

@ -500,11 +500,11 @@ brw_meta_fbo_stencil_blit(struct brw_context *brw,
.mirror_x = mirror_x, .mirror_y = mirror_y };
adjust_mip_level(dst_mt, dst_irb->mt_level, dst_irb->mt_layer, &dims);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
_mesa_meta_begin(ctx, MESA_META_ALL);
brw_meta_stencil_blit(brw,
dst_mt, dst_irb->mt_level, dst_irb->mt_layer, &dims);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}
void
@ -524,7 +524,7 @@ brw_meta_stencil_updownsample(struct brw_context *brw,
if (dst->stencil_mt)
dst = dst->stencil_mt;
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(1, &fbo);
@ -535,7 +535,7 @@ brw_meta_stencil_updownsample(struct brw_context *brw,
GL_RENDERBUFFER, rbo);
brw_meta_stencil_blit(brw, dst, 0, 0, &dims);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
_mesa_DeleteRenderbuffers(1, &rbo);
_mesa_DeleteFramebuffers(1, &fbo);

4
src/mesa/drivers/dri/i965/brw_meta_updownsample.c
View file

@ -116,7 +116,7 @@ brw_meta_updownsample(struct brw_context *brw,
blit_bit = GL_COLOR_BUFFER_BIT;
}
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(2, fbos);
@ -147,5 +147,5 @@ brw_meta_updownsample(struct brw_context *brw,
_mesa_meta_end(ctx);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}

2
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -580,7 +580,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
* non-pipelined state that will need the PIPE_CONTROL workaround.
*/
if (brw->gen == 6) {
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
}
unsigned int len;

8
src/mesa/drivers/dri/i965/brw_performance_monitor.c
View file

@ -581,7 +581,7 @@ snapshot_statistics_registers(struct brw_context *brw,
const int group = PIPELINE_STATS_COUNTERS;
const int num_counters = ctx->PerfMonitor.Groups[group].NumCounters;
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
for (int i = 0; i < num_counters; i++) {
if (BITSET_TEST(monitor->base.ActiveCounters[group], i)) {
@ -687,7 +687,7 @@ stop_oa_counters(struct brw_context *brw)
* The amount of batch space it takes to emit an MI_REPORT_PERF_COUNT snapshot,
* including the required PIPE_CONTROL flushes.
*
* Sandybridge is the worst case scenario: intel_batchbuffer_emit_mi_flush
* Sandybridge is the worst case scenario: brw_emit_mi_flush
* expands to three PIPE_CONTROLs which are 4 DWords each. We have to flush
* before and after MI_REPORT_PERF_COUNT, so multiply by two. Finally, add
* the 3 DWords for MI_REPORT_PERF_COUNT itself.
@ -713,7 +713,7 @@ emit_mi_report_perf_count(struct brw_context *brw,
int batch_used = brw->batch.used;
/* Reports apparently don't always get written unless we flush first. */
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
if (brw->gen == 5) {
/* Ironlake requires two MI_REPORT_PERF_COUNT commands to write all
@ -751,7 +751,7 @@ emit_mi_report_perf_count(struct brw_context *brw,
}
/* Reports apparently don't always get written unless we flush after. */
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
(void) batch_used;
assert(brw->batch.used - batch_used <= MI_REPORT_PERF_COUNT_BATCH_DWORDS * 4);

8
src/mesa/drivers/dri/i965/brw_pipe_control.c
View file

@ -189,7 +189,7 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
* already flushed (e.g., via a preceding MI_FLUSH).
*/
void
intel_emit_depth_stall_flushes(struct brw_context *brw)
brw_emit_depth_stall_flushes(struct brw_context *brw)
{
assert(brw->gen >= 6 && brw->gen <= 9);
@ -270,7 +270,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
* really our business. That leaves only stall at scoreboard.
*/
void
intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
{
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_CS_STALL |
@ -287,7 +287,7 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
* This is also used for the always_flush_cache driconf debug option.
*/
void
intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
brw_emit_mi_flush(struct brw_context *brw)
{
if (brw->batch.ring == BLT_RING && brw->gen >= 6) {
BEGIN_BATCH_BLT(4);
@ -321,7 +321,7 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
* Flush Enable =1, a PIPE_CONTROL with any non-zero
* post-sync-op is required.
*/
intel_emit_post_sync_nonzero_flush(brw);
brw_emit_post_sync_nonzero_flush(brw);
}
}
brw_emit_pipe_control_flush(brw, flags);

4
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -349,7 +349,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
return;
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
brw_emit_post_sync_nonzero_flush(brw);
brw_upload_invariant_state(brw);
@ -710,7 +710,7 @@ brw_upload_pipeline_state(struct brw_context *brw,
/* Emit Sandybridge workaround flushes on every primitive, for safety. */
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
brw_emit_post_sync_nonzero_flush(brw);
brw_upload_programs(brw, pipeline);
merge_ctx_state(brw, &state);

6
src/mesa/drivers/dri/i965/gen6_blorp.cpp
View file

@ -821,7 +821,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER */
{
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
BEGIN_BATCH(7);
/* 3DSTATE_DEPTH_BUFFER dw0 */
@ -896,7 +896,7 @@ static void
gen6_blorp_emit_depth_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@ -1021,7 +1021,7 @@ gen6_blorp_exec(struct brw_context *brw,
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
/* Emit workaround flushes when we switch from drawing to blorping. */
intel_emit_post_sync_nonzero_flush(brw);
brw_emit_post_sync_nonzero_flush(brw);
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,

2
src/mesa/drivers/dri/i965/gen6_depth_state.c
View file

@ -65,7 +65,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
*/
bool enable_hiz_ss = hiz || separate_stencil;
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
if (!irb)

6
src/mesa/drivers/dri/i965/gen6_queryobj.c
View file

@ -86,7 +86,7 @@ static void
write_primitives_generated(struct brw_context *brw,
drm_intel_bo *query_bo, int stream, int idx)
{
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
if (brw->gen >= 7 && stream > 0) {
brw_store_register_mem64(brw, query_bo,
@ -100,7 +100,7 @@ static void
write_xfb_primitives_written(struct brw_context *brw,
drm_intel_bo *bo, int stream, int idx)
{
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
if (brw->gen >= 7) {
brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream), idx);
@ -157,7 +157,7 @@ emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo,
/* Emit a flush to make sure various parts of the pipeline are complete and
* we get an accurate value
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
brw_store_register_mem64(brw, bo, reg, idx);
}

2
src/mesa/drivers/dri/i965/gen6_sol.c
View file

@ -292,5 +292,5 @@ brw_end_transform_feedback(struct gl_context *ctx,
* simplicity, just do a full flush.
*/
struct brw_context *brw = brw_context(ctx);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}

2
src/mesa/drivers/dri/i965/gen6_urb.c
View file

@ -120,7 +120,7 @@ gen6_upload_urb( struct brw_context *brw )
* a workaround.
*/
if (brw->urb.gs_present && !gs_present)
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
brw->urb.gs_present = gs_present;
}

4
src/mesa/drivers/dri/i965/gen7_blorp.cpp
View file

@ -645,7 +645,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER */
{
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@ -696,7 +696,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
static void
gen7_blorp_emit_depth_disable(struct brw_context *brw)
{
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));

2
src/mesa/drivers/dri/i965/gen7_misc_state.c
View file

@ -57,7 +57,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
return;
}
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
if (!irb)

4
src/mesa/drivers/dri/i965/gen7_sol_state.c
View file

@ -365,7 +365,7 @@ gen7_save_primitives_written_counters(struct brw_context *brw,
}
/* Flush any drawing so that the counters have the right values. */
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
/* Emit MI_STORE_REGISTER_MEM commands to write the values. */
for (int i = 0; i < streams; i++) {
@ -502,7 +502,7 @@ gen7_pause_transform_feedback(struct gl_context *ctx,
(struct brw_transform_feedback_object *) obj;
/* Flush any drawing so that the counters have the right values. */
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
/* Save the SOL buffer offset register values. */
if (brw->gen < 8) {

2
src/mesa/drivers/dri/i965/gen8_depth_state.c
View file

@ -57,7 +57,7 @@ emit_depth_packets(struct brw_context *brw,
return;
}
intel_emit_depth_stall_flushes(brw);
brw_emit_depth_stall_flushes(brw);
/* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
BEGIN_BATCH(8);

6
src/mesa/drivers/dri/i965/intel_blit.c
View file

@ -460,7 +460,7 @@ intelEmitCopyBlit(struct brw_context *brw,
ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
return true;
}
@ -544,7 +544,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
return true;
}
@ -667,5 +667,5 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}

4
src/mesa/drivers/dri/i965/intel_buffer_objects.c
View file

@ -560,7 +560,7 @@ brw_unmap_buffer(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
drm_intel_bo_unreference(intel_obj->range_map_bo[index]);
intel_obj->range_map_bo[index] = NULL;
@ -632,7 +632,7 @@ brw_copy_buffer_subdata(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}
void

6
src/mesa/drivers/dri/i965/intel_extensions.c
View file

@ -76,7 +76,7 @@ can_do_pipelined_register_writes(struct brw_context *brw)
OUT_BATCH(expected_value);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
/* Save the register's value back to the buffer. */
BEGIN_BATCH(3);
@ -132,7 +132,7 @@ can_write_oacontrol(struct brw_context *brw)
OUT_BATCH(expected_value);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
/* Save the register's value back to the buffer. */
BEGIN_BATCH(3);
@ -143,7 +143,7 @@ can_write_oacontrol(struct brw_context *brw)
offset * sizeof(uint32_t));
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
/* Set OACONTROL back to zero (everything off). */
BEGIN_BATCH(3);

2
src/mesa/drivers/dri/i965/intel_fbo.c
View file

@ -1076,7 +1076,7 @@ brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo)
if (!_mesa_set_search(brw->render_cache, bo))
return;
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
}
/**

2
src/mesa/drivers/dri/i965/intel_pixel_read.c
View file

@ -247,7 +247,7 @@ intelReadPixels(struct gl_context * ctx,
* rendered to via a PBO at any point, so it seems better to just
* flush here unconditionally.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
return;
}

2
src/mesa/drivers/dri/i965/intel_syncobj.c
View file

@ -69,7 +69,7 @@ brw_fence_insert(struct brw_context *brw, struct brw_fence *fence)
assert(!fence->batch_bo);
assert(!fence->signalled);
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
fence->batch_bo = brw->batch.bo;
drm_intel_bo_reference(fence->batch_bo);
intel_batchbuffer_flush(brw);

2
src/mesa/drivers/dri/i965/intel_tex_image.c
View file

@ -490,7 +490,7 @@ intel_get_tex_image(struct gl_context *ctx,
* See the related comment in intelReadPixels() for a more detailed
* explanation.
*/
intel_batchbuffer_emit_mi_flush(brw);
brw_emit_mi_flush(brw);
return;
}