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radeonsi: use conformant line rasterization
AA lines are not completely correct (see TODO), but everything else should be. + 3 linestipple piglits Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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789ed13284
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4b11ef23b4
4 changed files with 29 additions and 5 deletions
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@ -200,6 +200,14 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
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{
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int setup_samples = nr_samples > 1 ? nr_samples :
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overrast_samples > 1 ? overrast_samples : 0;
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/* Required by OpenGL line rasterization.
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*
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* TODO: We should also enable perpendicular endcaps for AA lines,
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* but that requires implementing line stippling in the pixel
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* shader. SC can only do line stippling with axis-aligned
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* endcaps.
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*/
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unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
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if (setup_samples > 1) {
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/* indexed by log2(nr_samples) */
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@ -215,7 +223,7 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
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util_logbase2(util_next_power_of_two(ps_iter_samples));
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radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
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radeon_emit(cs, S_028BDC_LAST_PIXEL(1) |
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radeon_emit(cs, sc_line_cntl |
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S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
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radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
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S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
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@ -242,7 +250,7 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
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}
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} else {
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radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
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radeon_emit(cs, S_028BDC_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
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radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
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radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
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radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
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@ -203,6 +203,12 @@
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#define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1) << 10)
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#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
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#define C_028BDC_LAST_PIXEL 0xFFFFFBFF
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#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1) << 11)
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#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
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#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
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#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1) << 12)
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#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
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#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
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#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0
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#define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x7) << 0)
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#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1) << 4)
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@ -3805,7 +3805,15 @@ static void si_init_config(struct si_context *sctx)
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S_028034_BR_X(16384) | S_028034_BR_Y(16384));
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si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
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si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
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si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
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S_028230_ER_TRI(0xA) |
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S_028230_ER_POINT(0xA) |
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S_028230_ER_RECT(0xA) |
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/* Required by DX10_DIAMOND_TEST_ENA: */
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S_028230_ER_LINE_LR(0x1A) |
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S_028230_ER_LINE_RL(0x26) |
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S_028230_ER_LINE_TB(0xA) |
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S_028230_ER_LINE_BT(0xA));
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/* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
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si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
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si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
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@ -429,10 +429,12 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
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rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
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return;
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/* For lines, reset the stipple pattern at each primitive. Otherwise,
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* reset the stipple pattern at each packet (line strips, line loops).
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*/
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radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
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rs->pa_sc_line_stipple |
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S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
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rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
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S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
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sctx->last_rast_prim = rast_prim;
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sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
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