From 4aec44ea919a5f5539db321cdccdb1e1eb9cc826 Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Tue, 2 Dec 2025 15:03:42 -0800 Subject: [PATCH] tu: Use appropriate chip variants for RB regs. Part-of: --- src/freedreno/vulkan/tu_cmd_buffer.cc | 10 ++++------ src/freedreno/vulkan/tu_pipeline.cc | 12 ++++++------ 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index aa3e6376765..043358a54f3 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -560,7 +560,7 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem) (a6xx_ccu_cache_size)(dev->physical_device->info->props.gmem_ccu_color_cache_fraction); if (CHIP == A7XX) { - tu_cs_emit_regs(cs, A7XX_RB_CCU_CACHE_CNTL( + tu_cs_emit_regs(cs, RB_CCU_CACHE_CNTL(CHIP, .depth_offset_hi = depth_offset_hi, .color_offset_hi = color_offset_hi, .depth_cache_size = CCU_CACHE_SIZE_FULL, @@ -855,9 +855,7 @@ tu6_emit_bin_size(struct tu_cs *cs, .lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, )); /* no flag for RB_RESOLVE_CNTL_3... */ - tu_cs_emit_regs(cs, - A6XX_RB_RESOLVE_CNTL_3(.binw = bin_w, - .binh = bin_h)); + tu_cs_emit_regs(cs, RB_RESOLVE_CNTL_3(CHIP, .binw = bin_w, .binh = bin_h)); } template @@ -2055,7 +2053,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_RB_RBP_CNTL, phys_dev->info->magic.RB_RBP_CNTL); if (CHIP >= A7XX) { - tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x7)); + tu_cs_emit_regs(cs, RB_UNKNOWN_8E09(CHIP, 0x7)); tu_cond_exec_end(cs); } @@ -2992,7 +2990,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, .rt7_sysmem = true, )); - tu_cs_emit_regs(cs, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_SYSMEM)); + tu_cs_emit_regs(cs, RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_SYSMEM)); } tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc index 81fb076dcb2..7739945f01c 100644 --- a/src/freedreno/vulkan/tu_pipeline.cc +++ b/src/freedreno/vulkan/tu_pipeline.cc @@ -2566,8 +2566,8 @@ tu6_emit_viewport(struct tu_cs *cs, } tu_cs_emit_regs(cs, - A6XX_RB_VIEWPORT_ZCLAMP_MIN(z_clamp_min), - A6XX_RB_VIEWPORT_ZCLAMP_MAX(z_clamp_max)); + RB_VIEWPORT_ZCLAMP_MIN(CHIP, z_clamp_min), + RB_VIEWPORT_ZCLAMP_MAX(CHIP, z_clamp_max)); } struct apply_viewport_state { @@ -3394,10 +3394,10 @@ tu6_emit_rast(struct tu_cs *cs, A6XX_GRAS_SU_POINT_SIZE(1.0f)); if (CHIP == A6XX && cs->device->physical_device->info->props.has_legacy_pipeline_shading_rate) { - tu_cs_emit_regs(cs, A6XX_RB_UNKNOWN_8A00()); - tu_cs_emit_regs(cs, A6XX_RB_UNKNOWN_8A10()); - tu_cs_emit_regs(cs, A6XX_RB_UNKNOWN_8A20()); - tu_cs_emit_regs(cs, A6XX_RB_UNKNOWN_8A30()); + tu_cs_emit_regs(cs, RB_UNKNOWN_8A00(CHIP)); + tu_cs_emit_regs(cs, RB_UNKNOWN_8A10(CHIP)); + tu_cs_emit_regs(cs, RB_UNKNOWN_8A20(CHIP)); + tu_cs_emit_regs(cs, RB_UNKNOWN_8A30(CHIP)); } }