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asahi: fix metadata for images with VS lowered to GS

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KHR-GL46.shader_image_load_store.basic-allTargets-atomicVS

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27616>
This commit is contained in:
Alyssa Rosenzweig 2023-12-09 22:22:57 -04:00 • committed by Marge Bot
parent 9753cd44f7
commit 4aadf67523
4 changed files with 35 additions and 20 deletions
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9
src/asahi/compiler/agx_compile.c
View file

@ -2922,9 +2922,13 @@ void
agx_preprocess_nir(nir_shader *nir, const nir_shader *libagx,
bool allow_mediump, struct agx_uncompiled_shader_info *out)
{
if (out)
if (out) {
memset(out, 0, sizeof(*out));
out->nr_bindful_textures = BITSET_LAST_BIT(nir->info.textures_used);
out->nr_bindful_images = BITSET_LAST_BIT(nir->info.images_used);
}
NIR_PASS(_, nir, nir_lower_vars_to_ssa);
/* Lower large arrays to scratch and small arrays to csel */
@ -3036,9 +3040,6 @@ agx_compile_shader_nir(nir_shader *nir, struct agx_shader_key *key,
"agx_preprocess_nir is called first, then the shader is specalized,"
"then the specialized shader is compiled");
out->nr_bindful_textures = BITSET_LAST_BIT(nir->info.textures_used);
out->nr_bindful_images = BITSET_LAST_BIT(nir->info.images_used);
/* If required, tag writes will be enabled by instruction selection */
if (nir->info.stage == MESA_SHADER_FRAGMENT)
out->tag_write_disable = !nir->info.writes_memory;

6
src/asahi/compiler/agx_compile.h
View file

@ -100,6 +100,9 @@ struct agx_uncompiled_shader_info {
uint64_t inputs_linear_shaded;
uint8_t cull_distance_size;
bool has_edgeflags;
/* Number of bindful textures, images used */
unsigned nr_bindful_textures, nr_bindful_images;
};
struct agx_shader_info {
@ -154,9 +157,6 @@ struct agx_shader_info {
bool uses_txf;
unsigned txf_sampler;
/* Number of bindful textures, images used */
unsigned nr_bindful_textures, nr_bindful_images;
/* Number of 16-bit registers used by the main shader and preamble
* respectively.
*/

4
src/asahi/lib/agx_nir_lower_gs.c
View file

@ -290,6 +290,10 @@ agx_nir_link_vs_gs(nir_shader *vs, nir_shader *gs)
/* Copy texture info. We force bindless on GS for now. */
gs->info.num_textures = vs->info.num_textures;
gs->info.num_images = vs->info.num_images;
BITSET_COPY(gs->info.textures_used, vs->info.textures_used);
BITSET_COPY(gs->info.textures_used_by_txf, vs->info.textures_used_by_txf);
BITSET_COPY(gs->info.images_used, vs->info.images_used);
/* Inline the VS into the GS */
nir_inline_functions(gs);

36
src/gallium/drivers/asahi/agx_state.c
View file

@ -2702,17 +2702,21 @@ agx_set_null_pbe(struct agx_pbe_packed *pbe, uint64_t sink)
}
static uint32_t
agx_nr_tex_descriptors_without_spilled_rts(const struct agx_compiled_shader *cs)
agx_nr_tex_descriptors_without_spilled_rts(
const struct agx_uncompiled_shader *cs)
{
if (!cs)
return 0;
/* 2 descriptors per image, 1 descriptor per texture */
return cs->info.nr_bindful_textures + (2 * cs->info.nr_bindful_images);
}
static uint32_t
agx_nr_tex_descriptors(struct agx_batch *batch, enum pipe_shader_type stage,
const struct agx_compiled_shader *cs)
agx_nr_tex_descriptors(struct agx_batch *batch, enum pipe_shader_type stage)
{
unsigned n = agx_nr_tex_descriptors_without_spilled_rts(cs);
unsigned n = agx_nr_tex_descriptors_without_spilled_rts(
batch->ctx->stage[stage].shader);
/* We add on texture/PBE descriptors for spilled render targets */
bool spilled_rt = stage == PIPE_SHADER_FRAGMENT &&
@ -2754,11 +2758,18 @@ agx_upload_textures(struct agx_batch *batch, struct agx_compiled_shader *cs,
enum pipe_shader_type stage)
{
struct agx_context *ctx = batch->ctx;
unsigned nr_textures = cs->info.nr_bindful_textures;
if (!ctx->stage[stage].shader) {
batch->texture_count[stage] = 0;
batch->textures[stage] = 0;
return;
}
unsigned nr_textures = ctx->stage[stage].shader->info.nr_bindful_textures;
unsigned nr_active_textures = ctx->stage[stage].texture_count;
unsigned nr_tex_descriptors = agx_nr_tex_descriptors(batch, stage, cs);
unsigned nr_images = cs->info.nr_bindful_images;
unsigned nr_tex_descriptors = agx_nr_tex_descriptors(batch, stage);
unsigned nr_images = ctx->stage[stage].shader->info.nr_bindful_images;
struct agx_ptr T_tex = agx_pool_alloc_aligned(
&batch->pool, AGX_TEXTURE_LENGTH * nr_tex_descriptors, 64);
@ -2790,8 +2801,7 @@ agx_upload_textures(struct agx_batch *batch, struct agx_compiled_shader *cs,
for (unsigned i = 0; i < nr_images; ++i) {
/* Image descriptors come in pairs after the textures */
struct agx_texture_packed *texture =
((struct agx_texture_packed *)T_tex.cpu) +
cs->info.nr_bindful_textures + (2 * i);
((struct agx_texture_packed *)T_tex.cpu) + nr_textures + (2 * i);
struct agx_pbe_packed *pbe = (struct agx_pbe_packed *)(texture + 1);
@ -2822,7 +2832,7 @@ agx_upload_textures(struct agx_batch *batch, struct agx_compiled_shader *cs,
struct agx_texture_packed *out =
((struct agx_texture_packed *)T_tex.cpu) +
agx_nr_tex_descriptors_without_spilled_rts(cs);
agx_nr_tex_descriptors_without_spilled_rts(ctx->stage[stage].shader);
agx_upload_spilled_rt_descriptors(out, batch);
}
@ -3386,7 +3396,7 @@ agx_encode_state(struct agx_batch *batch, uint8_t *out, bool is_lines,
cfg.uniform_register_count = vs->info.push_count;
cfg.preshader_register_count = vs->info.nr_preamble_gprs;
cfg.texture_state_register_count =
agx_nr_tex_descriptors(batch, PIPE_SHADER_VERTEX, vs);
agx_nr_tex_descriptors(batch, PIPE_SHADER_VERTEX);
cfg.sampler_state_register_count =
translate_sampler_state_count(ctx, vs, PIPE_SHADER_VERTEX);
}
@ -3583,7 +3593,7 @@ agx_encode_state(struct agx_batch *batch, uint8_t *out, bool is_lines,
cfg.uniform_register_count = ctx->fs->info.push_count;
cfg.preshader_register_count = ctx->fs->info.nr_preamble_gprs;
cfg.texture_state_register_count =
agx_nr_tex_descriptors(batch, PIPE_SHADER_FRAGMENT, ctx->fs);
agx_nr_tex_descriptors(batch, PIPE_SHADER_FRAGMENT);
cfg.sampler_state_register_count =
translate_sampler_state_count(ctx, ctx->fs, PIPE_SHADER_FRAGMENT);
cfg.cf_binding_count = ctx->fs->info.varyings.fs.nr_bindings;
@ -4973,7 +4983,7 @@ agx_launch(struct agx_batch *batch, const struct pipe_grid_info *info,
cfg.uniform_register_count = cs->info.push_count;
cfg.preshader_register_count = cs->info.nr_preamble_gprs;
cfg.texture_state_register_count =
agx_nr_tex_descriptors(batch, stage, cs);
agx_nr_tex_descriptors(batch, merged_stage(ctx, stage));
cfg.sampler_state_register_count =
translate_sampler_state_count(ctx, cs, stage);
cfg.pipeline =