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ir3: enable load/store_const_ir3 vectorization

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Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
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Job Noorman 2024-08-15 08:46:36 +02:00 • committed by Marge Bot
parent 9998b65695
commit 4a6d48cf4c
1 changed files with 7 additions and 1 deletions
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8
src/freedreno/ir3/ir3_nir.c
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@ -120,6 +120,12 @@ ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
struct ir3_compiler *compiler = data;
unsigned byte_size = bit_size / 8;
if (low->intrinsic == nir_intrinsic_load_const_ir3)
return bit_size <= 32 && num_components <= 4;
if (low->intrinsic == nir_intrinsic_store_const_ir3)
return bit_size == 32 && num_components <= 4;
/* Don't vectorize load_ssbo's that we could otherwise lower to isam,
* as the tex cache benefit outweighs the benefit of vectorizing. If we
* support isam.v, we can vectorize this though.
@ -317,7 +323,7 @@ ir3_optimize_loop(struct ir3_compiler *compiler, nir_shader *s)
progress |= OPT(s, nir_opt_offsets, &offset_options);
nir_load_store_vectorize_options vectorize_opts = {
.modes = nir_var_mem_ubo | nir_var_mem_ssbo,
.modes = nir_var_mem_ubo | nir_var_mem_ssbo | nir_var_uniform,
.callback = ir3_nir_should_vectorize_mem,
.robust_modes = compiler->options.robust_buffer_access2 ?
nir_var_mem_ubo | nir_var_mem_ssbo : 0,