mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-08 09:08:10 +02:00
nouveau/mme: Add a tiny simulator for the Turing+ MME
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24326>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
51e8194736
commit
4a5c0b686a
3 changed files with 599 additions and 0 deletions
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@ -38,6 +38,8 @@ libnouveau_mme_files = files(
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'mme_tu104.c',
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'mme_tu104.h',
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'mme_tu104_builder.c',
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'mme_tu104_sim.c',
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'mme_tu104_sim.h',
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)
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_libnouveau_mme = static_library(
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570
src/nouveau/mme/mme_tu104_sim.c
Normal file
570
src/nouveau/mme/mme_tu104_sim.c
Normal file
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@ -0,0 +1,570 @@
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#include "mme_tu104_sim.h"
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#include <inttypes.h>
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#include "mme_tu104.h"
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#include "util/u_math.h"
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#include "nvk_clc597.h"
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struct mme_tu104_sim {
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uint32_t param_count;
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const uint32_t *params;
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uint32_t load[2];
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/* Bound memory ranges */
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uint32_t mem_count;
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struct mme_tu104_sim_mem *mems;
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/* SET_MME_MEM_ADDRESS_A/B */
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uint64_t mem_addr;
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/* RAM, accessed by DREAD/DWRITE */
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struct {
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uint32_t data[MME_TU104_DRAM_COUNT];
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/* SET_MME_MEM_RAM_ADDRESS */
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uint32_t addr;
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} ram;
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struct {
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struct {
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uint32_t data[1024];
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uint64_t count;
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} read_fifo;
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} dma;
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/* NVC597_SET_MME_SHADOW_SCRATCH(i) */
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uint32_t scratch[256];
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struct {
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unsigned mthd:16;
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unsigned inc:4;
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bool has_mthd:1;
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unsigned _pad:5;
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unsigned data_len:8;
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uint32_t data[8];
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} mthd;
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uint32_t set_regs;
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uint32_t regs[23];
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uint32_t alu_res[2];
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uint32_t alu_carry;
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uint16_t ip;
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uint16_t next_ip;
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uint32_t loop_count;
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uint16_t loop_start;
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uint16_t loop_end;
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};
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static bool
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inst_loads_reg(const struct mme_tu104_inst *inst,
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enum mme_tu104_reg reg)
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{
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return inst->pred == reg ||
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inst->alu[0].src[0] == reg ||
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inst->alu[0].src[1] == reg ||
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inst->alu[1].src[0] == reg ||
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inst->alu[1].src[1] == reg;
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}
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static bool
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inst_loads_out(const struct mme_tu104_inst *inst,
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enum mme_tu104_out_op out)
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{
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return inst->out[0].mthd == out ||
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inst->out[0].emit == out ||
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inst->out[1].mthd == out ||
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inst->out[1].emit == out;
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}
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static void
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load_params(struct mme_tu104_sim *sim,
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const struct mme_tu104_inst *inst)
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{
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const bool has_load0 = inst_loads_reg(inst, MME_TU104_REG_LOAD0) ||
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inst_loads_out(inst, MME_TU104_OUT_OP_LOAD0);
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const bool has_load1 = inst_loads_reg(inst, MME_TU104_REG_LOAD1) ||
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inst_loads_out(inst, MME_TU104_OUT_OP_LOAD1);
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assert(has_load0 || !has_load1);
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if (has_load0) {
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sim->load[0] = *sim->params;
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sim->params++;
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sim->param_count--;
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}
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if (has_load1) {
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sim->load[1] = *sim->params;
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sim->params++;
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sim->param_count--;
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}
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}
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static uint32_t
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load_state(struct mme_tu104_sim *sim, uint16_t state)
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{
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assert(state % 4 == 0);
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if (NVC597_SET_MME_SHADOW_SCRATCH(0) <= state &&
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state < NVC597_CALL_MME_MACRO(0)) {
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uint32_t i = (state - NVC597_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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return sim->scratch[i];
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}
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return 0;
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}
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static uint32_t *
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find_mem(struct mme_tu104_sim *sim, uint64_t addr, const char *op_desc)
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{
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for (uint32_t i = 0; i < sim->mem_count; i++) {
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if (addr < sim->mems[i].addr)
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continue;
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uint64_t offset = addr - sim->mems[i].addr;
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if (offset >= sim->mems[i].size)
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continue;
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assert(sim->mems[i].data != NULL);
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return (uint32_t *)((char *)sim->mems[i].data + offset);
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}
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fprintf(stderr, "FAULT in %s at address 0x%"PRIx64"\n", op_desc, addr);
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abort();
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}
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static void
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finish_dma_read_fifo(struct mme_tu104_sim *sim)
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{
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if (sim->dma.read_fifo.count == 0)
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return;
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for (uint32_t i = 0; i < sim->dma.read_fifo.count; i++) {
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uint32_t *src = find_mem(sim, sim->mem_addr + i * 4,
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"MME_DMA_READ_FIFOED");
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assert(src != NULL);
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sim->dma.read_fifo.data[i] = *src;
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}
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sim->param_count = sim->dma.read_fifo.count;
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sim->params = sim->dma.read_fifo.data;
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}
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static void
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flush_mthd(struct mme_tu104_sim *sim)
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{
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if (!sim->mthd.has_mthd)
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return;
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uint16_t mthd = sim->mthd.mthd;
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const uint32_t *p = sim->mthd.data;
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const uint32_t *end = sim->mthd.data + sim->mthd.data_len;
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while (p < end) {
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uint32_t dw_used = 1;
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if (NVC597_SET_MME_SHADOW_SCRATCH(0) <= mthd &&
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mthd < NVC597_CALL_MME_MACRO(0)) {
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uint32_t i = (mthd - NVC597_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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sim->scratch[i] = *p;
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} else {
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switch (mthd) {
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case NVC597_SET_REPORT_SEMAPHORE_A: {
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assert(p + 4 <= end);
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uint64_t addr = ((uint64_t)p[0] << 32) | p[1];
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uint32_t data = p[2];
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assert(p[3] == 0x10000000);
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dw_used = 4;
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uint32_t *mem = find_mem(sim, addr, "SET_REPORT_SEMAPHORE");
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*mem = data;
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break;
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}
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case NVC597_SET_MME_DATA_RAM_ADDRESS:
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sim->ram.addr = *p;
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break;
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case NVC597_SET_MME_MEM_ADDRESS_A:
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assert(p + 2 <= end);
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sim->mem_addr = ((uint64_t)p[0] << 32) | p[1];
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dw_used = 2;
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break;
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case NVC597_MME_DMA_READ_FIFOED:
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sim->dma.read_fifo.count = *p;
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break;
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default:
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fprintf(stdout, "%s:\n", P_PARSE_NVC597_MTHD(mthd));
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P_DUMP_NVC597_MTHD_DATA(mthd, *p, " ");
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break;
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}
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}
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p += dw_used;
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assert(sim->mthd.inc == 1);
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mthd += dw_used * 4;
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}
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sim->mthd.has_mthd = false;
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}
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static void
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eval_extended(struct mme_tu104_sim *sim,
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uint32_t x, uint32_t y)
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{
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/* The only extended method we know about appears to be some sort of
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* barrier required when using READ_FIFOED.
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*/
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assert(x == 0x1000);
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assert(y == 1);
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flush_mthd(sim);
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finish_dma_read_fifo(sim);
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}
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static uint32_t
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load_reg(struct mme_tu104_sim *sim,
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const struct mme_tu104_inst *inst,
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uint32_t imm_idx, enum mme_tu104_reg reg)
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{
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if (reg <= MME_TU104_REG_R23) {
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assert(sim->set_regs & BITFIELD_BIT(reg));
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return sim->regs[reg];
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}
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switch (reg) {
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case MME_TU104_REG_ZERO:
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return 0;
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case MME_TU104_REG_IMM:
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assert(imm_idx < 2);
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/* Immediates are treated as signed for ALU ops */
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return (int16_t)inst->imm[imm_idx];
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case MME_TU104_REG_IMMPAIR:
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assert(imm_idx < 2);
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/* Immediates are treated as signed for ALU ops */
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return (int16_t)inst->imm[1 - imm_idx];
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case MME_TU104_REG_IMM32:
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return ((uint32_t)inst->imm[0] << 16) | inst->imm[1];
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case MME_TU104_REG_LOAD0:
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return sim->load[0];
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case MME_TU104_REG_LOAD1:
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return sim->load[1];
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default:
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unreachable("Unhandled register type");
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}
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}
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static uint8_t
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load_pred(struct mme_tu104_sim *sim,
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const struct mme_tu104_inst *inst)
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{
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if (inst->pred_mode == MME_TU104_PRED_UUUU)
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return 0xf;
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uint32_t val = load_reg(sim, inst, -1, inst->pred);
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const char *pred = mme_tu104_pred_to_str(inst->pred_mode);
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uint8_t mask = 0;
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for (unsigned i = 0; i < 4; i++) {
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if (pred[i] != (val ? 'T' : 'F'))
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mask |= BITFIELD_BIT(i);
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}
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return mask;
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}
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static void
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store_reg(struct mme_tu104_sim *sim,
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enum mme_tu104_reg reg,
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uint32_t val)
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{
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if (reg <= MME_TU104_REG_R23) {
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sim->set_regs |= BITFIELD_BIT(reg);
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sim->regs[reg] = val;
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} else if (reg <= MME_TU104_REG_ZERO) {
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/* Do nothing */
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} else {
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unreachable("Unhandled register type");
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}
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}
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static bool
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eval_cond(enum mme_tu104_alu_op op, uint32_t x, uint32_t y)
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{
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switch (op) {
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case MME_TU104_ALU_OP_BLT:
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case MME_TU104_ALU_OP_SLT:
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return (int32_t)x < (int32_t)y;
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case MME_TU104_ALU_OP_BLTU:
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case MME_TU104_ALU_OP_SLTU:
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return (uint32_t)x < (uint32_t)y;
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case MME_TU104_ALU_OP_BLE:
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case MME_TU104_ALU_OP_SLE:
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return (int32_t)x <= (int32_t)y;
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case MME_TU104_ALU_OP_BLEU:
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case MME_TU104_ALU_OP_SLEU:
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return (uint32_t)x <= (uint32_t)y;
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case MME_TU104_ALU_OP_BEQ:
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case MME_TU104_ALU_OP_SEQ:
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return x == y;
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default:
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unreachable("Not a comparison op");
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}
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}
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static void
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eval_alu(struct mme_tu104_sim *sim,
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const struct mme_tu104_inst *inst,
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uint32_t alu_idx)
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{
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const struct mme_tu104_alu *alu = &inst->alu[alu_idx];
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const uint32_t x = load_reg(sim, inst, alu_idx, alu->src[0]);
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const uint32_t y = load_reg(sim, inst, alu_idx, alu->src[1]);
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uint32_t res = 0;
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switch (inst->alu[alu_idx].op) {
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case MME_TU104_ALU_OP_ADD:
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res = x + y;
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sim->alu_carry = res < x;
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break;
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case MME_TU104_ALU_OP_ADDC:
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assert(alu_idx == 1);
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assert(inst->alu[0].op == MME_TU104_ALU_OP_ADD);
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res = x + y + sim->alu_carry;
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break;
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case MME_TU104_ALU_OP_SUB:
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res = x - y;
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sim->alu_carry = res > x;
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break;
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case MME_TU104_ALU_OP_SUBB:
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assert(alu_idx == 1);
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assert(inst->alu[0].op == MME_TU104_ALU_OP_SUB);
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res = x - y - sim->alu_carry;
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break;
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case MME_TU104_ALU_OP_MUL: {
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/* Sign extend but use uint64_t for the multiply so that we avoid
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* undefined behavior from possible signed multiply roll-over.
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*/
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const uint64_t x_u64 = (int64_t)(int32_t)x;
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const uint64_t y_u64 = (int64_t)(int32_t)y;
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const uint64_t xy_u64 = x_u64 * y_u64;
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res = xy_u64;
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sim->alu_carry = xy_u64 >> 32;
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break;
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}
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case MME_TU104_ALU_OP_MULH:
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assert(inst->alu[alu_idx].src[0] == MME_TU104_REG_ZERO);
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assert(inst->alu[alu_idx].src[1] == MME_TU104_REG_ZERO);
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res = sim->alu_carry;
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break;
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case MME_TU104_ALU_OP_MULU: {
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const uint64_t x_u64 = x;
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const uint64_t y_u64 = y;
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const uint64_t xy_u64 = x_u64 * y_u64;
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res = xy_u64;
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sim->alu_carry = xy_u64 >> 32;
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break;
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}
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case MME_TU104_ALU_OP_EXTENDED:
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eval_extended(sim, x, y);
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break;
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case MME_TU104_ALU_OP_CLZ:
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res = __builtin_clz(x);
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break;
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case MME_TU104_ALU_OP_SLL:
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res = x << (y & 31);
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break;
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case MME_TU104_ALU_OP_SRL:
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res = x >> (y & 31);
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break;
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case MME_TU104_ALU_OP_SRA:
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res = (int32_t)x >> (y & 31);
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break;
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case MME_TU104_ALU_OP_AND:
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res = x & y;
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break;
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case MME_TU104_ALU_OP_NAND:
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res = ~(x & y);
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break;
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case MME_TU104_ALU_OP_OR:
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res = x | y;
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break;
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case MME_TU104_ALU_OP_XOR:
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res = x ^ y;
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break;
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case MME_TU104_ALU_OP_MERGE: {
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uint16_t immed = inst->imm[alu_idx];
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uint32_t dst_pos = (immed >> 10) & 0x3f;
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uint32_t bits = (immed >> 5) & 0x1f;
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uint32_t src_pos = (immed >> 0) & 0x1f;
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res = (x & ~(BITFIELD_MASK(bits) << dst_pos)) |
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(((y >> src_pos) & BITFIELD_MASK(bits)) << dst_pos);
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break;
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}
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case MME_TU104_ALU_OP_SLT:
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case MME_TU104_ALU_OP_SLTU:
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case MME_TU104_ALU_OP_SLE:
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case MME_TU104_ALU_OP_SLEU:
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case MME_TU104_ALU_OP_SEQ:
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res = eval_cond(inst->alu[alu_idx].op, x, y) ? ~0u : 0u;
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break;
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case MME_TU104_ALU_OP_STATE:
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flush_mthd(sim);
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res = load_state(sim, (uint16_t)(x + y) * 4);
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break;
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case MME_TU104_ALU_OP_LOOP:
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assert(sim->loop_count == 0);
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assert(inst->alu[alu_idx].dst == MME_TU104_REG_ZERO);
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assert(inst->alu[alu_idx].src[1] == MME_TU104_REG_ZERO);
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sim->loop_count = MAX2(1, x) - 1;
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sim->loop_start = sim->ip;
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sim->loop_end = sim->ip + inst->imm[alu_idx] - 1;
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assert(sim->loop_end > sim->ip);
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break;
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case MME_TU104_ALU_OP_JAL: {
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assert(inst->alu[alu_idx].dst == MME_TU104_REG_ZERO);
|
||||
assert(inst->alu[alu_idx].src[0] == MME_TU104_REG_ZERO);
|
||||
assert(inst->alu[alu_idx].src[1] == MME_TU104_REG_ZERO);
|
||||
/* No idea what bit 15 does. The NVIDIA blob always sets it. */
|
||||
assert(inst->imm[alu_idx] & BITFIELD_BIT(15));
|
||||
uint16_t offset = (inst->imm[alu_idx] & BITFIELD_MASK(15));
|
||||
sim->next_ip = sim->ip + offset;
|
||||
res = 0;
|
||||
break;
|
||||
}
|
||||
case MME_TU104_ALU_OP_BLT:
|
||||
case MME_TU104_ALU_OP_BLTU:
|
||||
case MME_TU104_ALU_OP_BLE:
|
||||
case MME_TU104_ALU_OP_BLEU:
|
||||
case MME_TU104_ALU_OP_BEQ: {
|
||||
assert(inst->alu[alu_idx].dst == MME_TU104_REG_ZERO);
|
||||
bool expect = (inst->imm[alu_idx] & BITFIELD_BIT(15)) != 0;
|
||||
if (eval_cond(inst->alu[alu_idx].op, x, y) == expect) {
|
||||
int16_t offset = util_mask_sign_extend(inst->imm[alu_idx], 13);
|
||||
assert((int)sim->ip + offset >= 0);
|
||||
assert((int)sim->ip + offset < 0x1000);
|
||||
sim->next_ip = sim->ip + offset;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case MME_TU104_ALU_OP_DREAD:
|
||||
assert(inst->alu[alu_idx].src[1] == MME_TU104_REG_ZERO);
|
||||
assert(x < ARRAY_SIZE(sim->ram.data));
|
||||
res = sim->ram.data[x];
|
||||
break;
|
||||
case MME_TU104_ALU_OP_DWRITE:
|
||||
assert(inst->alu[alu_idx].dst == MME_TU104_REG_ZERO);
|
||||
assert(x < ARRAY_SIZE(sim->ram.data));
|
||||
sim->ram.data[x] = y;
|
||||
break;
|
||||
default:
|
||||
unreachable("Unhandled ALU op");
|
||||
}
|
||||
|
||||
sim->alu_res[alu_idx] = res;
|
||||
store_reg(sim, inst->alu[alu_idx].dst, res);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
load_out(struct mme_tu104_sim *sim,
|
||||
const struct mme_tu104_inst *inst,
|
||||
enum mme_tu104_out_op op)
|
||||
{
|
||||
switch (op) {
|
||||
case MME_TU104_OUT_OP_ALU0:
|
||||
return sim->alu_res[0];
|
||||
case MME_TU104_OUT_OP_ALU1:
|
||||
return sim->alu_res[1];
|
||||
case MME_TU104_OUT_OP_LOAD0:
|
||||
return sim->load[0];
|
||||
case MME_TU104_OUT_OP_LOAD1:
|
||||
return sim->load[1];
|
||||
case MME_TU104_OUT_OP_IMM0:
|
||||
return inst->imm[0];
|
||||
case MME_TU104_OUT_OP_IMM1:
|
||||
return inst->imm[1];
|
||||
case MME_TU104_OUT_OP_IMMHIGH0:
|
||||
return inst->imm[0] >> 12;
|
||||
case MME_TU104_OUT_OP_IMMHIGH1:
|
||||
return inst->imm[1] >> 12;
|
||||
case MME_TU104_OUT_OP_IMM32:
|
||||
return ((uint32_t)inst->imm[0] << 16) | inst->imm[1];
|
||||
default:
|
||||
unreachable("Unhandled output op");
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
eval_out(struct mme_tu104_sim *sim,
|
||||
const struct mme_tu104_inst *inst,
|
||||
uint32_t out_idx)
|
||||
{
|
||||
if (inst->out[out_idx].mthd != MME_TU104_OUT_OP_NONE) {
|
||||
uint32_t data = load_out(sim, inst, inst->out[out_idx].mthd);
|
||||
|
||||
flush_mthd(sim);
|
||||
sim->mthd.mthd = (data & 0xfff) << 2;
|
||||
sim->mthd.inc = (data >> 12) & 0xf;
|
||||
sim->mthd.has_mthd = true;
|
||||
sim->mthd.data_len = 0;
|
||||
}
|
||||
|
||||
if (inst->out[out_idx].emit != MME_TU104_OUT_OP_NONE) {
|
||||
uint32_t data = load_out(sim, inst, inst->out[out_idx].emit);
|
||||
|
||||
assert(sim->mthd.data_len < ARRAY_SIZE(sim->mthd.data));
|
||||
sim->mthd.data[sim->mthd.data_len++] = data;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
mme_tu104_sim(uint32_t inst_count, const struct mme_tu104_inst *insts,
|
||||
uint32_t param_count, const uint32_t *params,
|
||||
uint32_t mem_count, struct mme_tu104_sim_mem *mems)
|
||||
{
|
||||
struct mme_tu104_sim sim = {
|
||||
.param_count = param_count,
|
||||
.params = params,
|
||||
.mem_count = mem_count,
|
||||
.mems = mems,
|
||||
};
|
||||
|
||||
bool end_next = false;
|
||||
while (true) {
|
||||
assert(sim.ip < inst_count);
|
||||
const struct mme_tu104_inst *inst = &insts[sim.ip];
|
||||
sim.next_ip = sim.ip + 1;
|
||||
|
||||
load_params(&sim, inst);
|
||||
|
||||
uint8_t pred = load_pred(&sim, inst);
|
||||
|
||||
/* No idea why the HW has this rule but it does */
|
||||
assert(inst->alu[0].op != MME_TU104_ALU_OP_STATE ||
|
||||
inst->alu[1].op != MME_TU104_ALU_OP_STATE);
|
||||
|
||||
if (pred & BITFIELD_BIT(0))
|
||||
eval_alu(&sim, inst, 0);
|
||||
if (pred & BITFIELD_BIT(1))
|
||||
eval_alu(&sim, inst, 1);
|
||||
if (pred & BITFIELD_BIT(2))
|
||||
eval_out(&sim, inst, 0);
|
||||
if (pred & BITFIELD_BIT(3))
|
||||
eval_out(&sim, inst, 1);
|
||||
|
||||
if (end_next)
|
||||
break;
|
||||
|
||||
end_next = inst->end_next;
|
||||
|
||||
if (sim.loop_count > 0 && sim.ip == sim.loop_end) {
|
||||
sim.loop_count--;
|
||||
sim.next_ip = sim.loop_start + 1;
|
||||
}
|
||||
|
||||
sim.ip = sim.next_ip;
|
||||
}
|
||||
|
||||
flush_mthd(&sim);
|
||||
}
|
||||
27
src/nouveau/mme/mme_tu104_sim.h
Normal file
27
src/nouveau/mme/mme_tu104_sim.h
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
#ifndef MME_TU104_SIM_H
|
||||
#define MME_TU104_SIM_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct mme_tu104_inst;
|
||||
|
||||
struct mme_tu104_sim_mem {
|
||||
uint64_t addr;
|
||||
void *data;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
void mme_tu104_sim(uint32_t inst_count, const struct mme_tu104_inst *insts,
|
||||
uint32_t param_count, const uint32_t *params,
|
||||
uint32_t mem_count, struct mme_tu104_sim_mem *mems);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MME_TU104_SIM_H */
|
||||
Loading…
Add table
Reference in a new issue