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freedreno/ir3: track # of driver params

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To avoid emitting unneeded const state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark 2019-08-01 14:22:46 -07:00
parent 7f1e3391c6
commit 4a188e4215
3 changed files with 35 additions and 11 deletions
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41
src/freedreno/ir3/ir3_nir.c
View file

@ -335,6 +335,24 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
} else {
layout->num_ubos = shader->info.num_ubos;
}
break;
case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_first_vertex:
layout->num_driver_params =
MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
break;
case nir_intrinsic_load_user_clip_plane:
layout->num_driver_params =
MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
break;
case nir_intrinsic_load_num_work_groups:
layout->num_driver_params =
MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
break;
case nir_intrinsic_load_local_group_size:
layout->num_driver_params =
MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
break;
default:
break;
}
@ -353,8 +371,17 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
ir3_nir_scan_driver_consts(nir, const_state);
if ((compiler->gpu_id < 500) &&
(shader->stream_output.num_outputs > 0)) {
const_state->num_driver_params =
MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
}
/* num_driver_params is scalar, align to vec4: */
const_state->num_driver_params = align(const_state->num_driver_params, 4);
debug_assert((shader->ubo_state.size % 16) == 0);
unsigned constoff = align(shader->ubo_state.size / 16, 4);
unsigned constoff = align(shader->ubo_state.size / 16, 8);
unsigned ptrsz = ir3_pointer_size(compiler);
if (const_state->num_ubos > 0) {
@ -374,15 +401,9 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
constoff += align(cnt, 4) / 4;
}
unsigned num_driver_params = 0;
if (shader->type == MESA_SHADER_VERTEX) {
num_driver_params = IR3_DP_VS_COUNT;
} else if (shader->type == MESA_SHADER_COMPUTE) {
num_driver_params = IR3_DP_CS_COUNT;
}
const_state->offsets.driver_param = constoff;
constoff += align(num_driver_params, 4) / 4;
if (const_state->num_driver_params > 0)
const_state->offsets.driver_param = constoff;
constoff += const_state->num_driver_params / 4;
if ((shader->type == MESA_SHADER_VERTEX) &&
(compiler->gpu_id < 500) &&

1
src/freedreno/ir3/ir3_shader.h
View file

@ -112,6 +112,7 @@ enum ir3_driver_param {
*/
struct ir3_const_state {
unsigned num_ubos;
unsigned num_driver_params; /* scalar */
struct {
/* user const start at zero */

4
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
View file

@ -532,6 +532,8 @@ ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
vertex_params_size = ARRAY_SIZE(vertex_params);
}
vertex_params_size = MAX2(vertex_params_size, const_state->num_driver_params);
bool needs_vtxid_base =
ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);
@ -656,7 +658,7 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
[IR3_DP_LOCAL_GROUP_SIZE_Y] = info->block[1],
[IR3_DP_LOCAL_GROUP_SIZE_Z] = info->block[2],
};
uint32_t size = MIN2(ARRAY_SIZE(compute_params),
uint32_t size = MIN2(const_state->num_driver_params,
v->constlen * 4 - offset * 4);
emit_const(ctx->screen, ring, v, offset * 4, 0, size,