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freedreno: Introduce common device info struct
This will collect all the various alignments, sizes, and magic values and set them appropriately, replacing the various pieces scattered throughout the drivers. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7385>
This commit is contained in:
Connor Abbott
Marge Bot
parent
ea81889ea4
commit
4a0bdf47e4
3 changed files with 186 additions and 0 deletions
117
src/freedreno/common/freedreno_dev_info.c
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117
src/freedreno/common/freedreno_dev_info.c
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@ -0,0 +1,117 @@
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/*
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* Copyright © 2020 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "freedreno_dev_info.h"
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#include "util/macros.h"
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static inline unsigned
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max_bitfield_val(unsigned high, unsigned low, unsigned shift)
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{
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return BITFIELD_MASK(high - low) << shift;
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}
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void
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freedreno_dev_info_init(struct freedreno_dev_info *info, uint32_t gpu_id)
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{
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if (gpu_id >= 600) {
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info->gmem_align_w = 16;
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info->gmem_align_h = 4;
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info->tile_align_w = gpu_id == 650 ? 96 : 32;
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info->tile_align_h = 32;
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/* based on GRAS_BIN_CONTROL: */
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info->tile_max_w = 1024; /* max_bitfield_val(5, 0, 5) */
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info->tile_max_h = max_bitfield_val(14, 8, 4);
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info->num_vsc_pipes = 32;
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switch (gpu_id) {
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case 615:
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case 618:
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info->a6xx.ccu_offset_gmem = 0x7c000;
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info->a6xx.ccu_offset_bypass = 0x10000;
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info->a6xx.ccu_cntl_gmem_unk2 = true;
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info->a6xx.supports_multiview_mask = false;
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info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x00100000;
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info->a6xx.magic.PC_UNKNOWN_9805 = 0;
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info->a6xx.magic.SP_UNKNOWN_A0F8 = 0;
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break;
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case 630:
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info->a6xx.ccu_offset_gmem = 0xf8000;
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info->a6xx.ccu_offset_bypass = 0x20000;
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info->a6xx.ccu_cntl_gmem_unk2 = true;
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info->a6xx.supports_multiview_mask = false;
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info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x01000000;
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info->a6xx.magic.PC_UNKNOWN_9805 = 1;
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info->a6xx.magic.SP_UNKNOWN_A0F8 = 1;
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break;
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case 640:
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info->a6xx.ccu_offset_gmem = 0xf8000;
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info->a6xx.ccu_offset_bypass = 0x20000;
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info->a6xx.supports_multiview_mask = true;
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info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x00100000;
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info->a6xx.magic.PC_UNKNOWN_9805 = 1;
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info->a6xx.magic.SP_UNKNOWN_A0F8 = 1;
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break;
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case 650:
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info->a6xx.ccu_offset_gmem = 0x114000;
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info->a6xx.ccu_offset_bypass = 0x30000;
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info->a6xx.supports_multiview_mask = true;
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info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x04100000;
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info->a6xx.magic.PC_UNKNOWN_9805 = 2;
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info->a6xx.magic.SP_UNKNOWN_A0F8 = 2;
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break;
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default:
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/* Drivers should be doing their own version filtering, so we
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* should never get here.
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*/
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unreachable("missing a6xx config");
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}
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} else if (gpu_id >= 500) {
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info->gmem_align_w = info->tile_align_w = 64;
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info->gmem_align_h = info->tile_align_h = 32;
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/* based on VSC_BIN_SIZE: */
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info->tile_max_w = 1024; /* max_bitfield_val(7, 0, 5) */
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info->tile_max_h = max_bitfield_val(16, 9, 5);
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info->num_vsc_pipes = 16;
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} else if (gpu_id >= 400) {
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info->gmem_align_w = info->tile_align_w = 32;
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info->gmem_align_h = info->tile_align_h = 32;
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/* based on VSC_BIN_SIZE: */
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info->tile_max_w = 1024; /* max_bitfield_val(4, 0, 5) */
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info->tile_max_h = max_bitfield_val(9, 5, 5);
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info->num_vsc_pipes = 8;
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} else if (gpu_id >= 300) {
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info->gmem_align_w = info->tile_align_w = 32;
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info->gmem_align_h = info->tile_align_h = 32;
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/* based on VSC_BIN_SIZE: */
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info->tile_max_w = 992; /* max_bitfield_val(4, 0, 5) */
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info->tile_max_h = max_bitfield_val(9, 5, 5);
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info->num_vsc_pipes = 8;
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} else {
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info->gmem_align_w = info->tile_align_w = 32;
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info->gmem_align_h = info->tile_align_h = 32;
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info->tile_max_w = 512;
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info->tile_max_h = ~0; /* TODO */
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info->num_vsc_pipes = 8;
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}
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}
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67
src/freedreno/common/freedreno_dev_info.h
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67
src/freedreno/common/freedreno_dev_info.h
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@ -0,0 +1,67 @@
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/*
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* Copyright © 2020 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef FREEDRENO_DEVICE_INFO_H
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#define FREEDRENO_DEVICE_INFO_H
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#include <stdint.h>
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#include <stdbool.h>
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/**
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* Freedreno hardware description and quirks
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*/
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struct freedreno_dev_info {
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/* alignment for size of tiles */
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uint32_t tile_align_w, tile_align_h;
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/* gmem load/store granularity */
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uint32_t gmem_align_w, gmem_align_h;
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/* max tile size */
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uint32_t tile_max_w, tile_max_h;
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uint32_t num_vsc_pipes;
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union {
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struct {
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/* Whether the PC_MULTIVIEW_MASK register exists. */
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bool supports_multiview_mask;
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/* info for setting RB_CCU_CNTL */
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uint32_t ccu_offset_gmem;
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uint32_t ccu_offset_bypass;
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bool ccu_cntl_gmem_unk2;
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struct {
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uint32_t RB_UNKNOWN_8E04_blit;
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uint32_t PC_UNKNOWN_9805;
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uint32_t SP_UNKNOWN_A0F8;
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} magic;
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} a6xx;
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};
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};
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void freedreno_dev_info_init(struct freedreno_dev_info *info, uint32_t gpu_id);
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#endif /* FREEDRENO_DEVICE_INFO_H */
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@ -22,6 +22,8 @@ libfreedreno_common = static_library(
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'freedreno_common',
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[
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'disasm.h',
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'freedreno_dev_info.c',
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'freedreno_dev_info.h',
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'freedreno_uuid.c',
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'freedreno_uuid.h',
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'freedreno_guardband.h',
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