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gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE

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FORCE_TILING should disable it. It has no effect now, but that may change
soon.

Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-11-11 21:14:03 +01:00
parent 44a3f2ee09
commit 49fa4a4e60
3 changed files with 6 additions and 1 deletions
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2
src/gallium/drivers/radeon/r600_texture.c
View file

@ -253,6 +253,8 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
if (is_imported)
flags |= RADEON_SURF_IMPORTED;
if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
array_mode, surface);

1
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -281,6 +281,7 @@ enum radeon_micro_mode {
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24)
#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
struct radeon_surf_level {
uint64_t offset;

4
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -402,7 +402,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
* requested, because TC-compatible HTILE requires 2D tiling.
*/
AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible &&
!(flags & RADEON_SURF_FMASK);
!AddrSurfInfoIn.flags.fmask &&
tex->nr_samples <= 1 &&
(flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
/* DCC notes:
* - If we add MSAA support, keep in mind that CB can't decompress 8bpp