diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 5e901dfac71..33b13a4cf09 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -301,38 +301,9 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
       if (irb == NULL || irb->mt == NULL)
          continue;
 
-      struct intel_mipmap_tree *mt = irb->mt;
-
-      /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
-       * the single-sampled color renderbuffers because the CCS buffer isn't
-       * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
-       * enabled because otherwise the surface state will be programmed with
-       * the linear equivalent format anyway.
-       */
-      if (brw->gen >= 9 && ctx->Color.sRGBEnabled && mt->num_samples <= 1 &&
-          _mesa_get_srgb_format_linear(mt->format) != mt->format) {
-
-         /* Lossless compression is not supported for SRGB formats, it
-          * should be impossible to get here with such surfaces.
-          */
-         assert(!intel_miptree_is_lossless_compressed(brw, mt));
-         intel_miptree_all_slices_resolve_color(brw, mt, 0);
-         brw_render_cache_set_check_flush(brw, mt->bo);
-      }
-
-      /* For layered rendering non-compressed fast cleared buffers need to be
-       * resolved. Surface state can carry only one fast color clear value
-       * while each layer may have its own fast clear color value. For
-       * compressed buffers color value is available in the color buffer.
-       */
-      if (irb->layer_count > 1 &&
-          !(irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
-          !intel_miptree_is_lossless_compressed(brw, mt)) {
-         assert(brw->gen >= 8);
-
-         intel_miptree_resolve_color(brw, mt, irb->mt_level, 1,
-                                     irb->mt_layer, irb->layer_count, 0);
-      }
+      intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
+                                   irb->mt_layer, irb->layer_count,
+                                   ctx->Color.sRGBEnabled);
    }
 
    _mesa_lock_context_textures(ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 3a1bb5023e4..07f1d48ff65 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -400,8 +400,8 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
          continue;
      
       brw_render_cache_set_add_bo(brw, irb->mt->bo);
-      intel_miptree_used_for_rendering(
-         brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count);
+      intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
+                                  irb->mt_layer, irb->layer_count);
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 033dd80e121..cd713b93e3f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2454,6 +2454,54 @@ intel_miptree_prepare_texture(struct brw_context *brw,
       *aux_supported_out = aux_supported;
 }
 
+void
+intel_miptree_prepare_render(struct brw_context *brw,
+                             struct intel_mipmap_tree *mt, uint32_t level,
+                             uint32_t start_layer, uint32_t layer_count,
+                             bool srgb_enabled)
+{
+   /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
+    * the single-sampled color renderbuffers because the CCS buffer isn't
+    * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
+    * enabled because otherwise the surface state will be programmed with
+    * the linear equivalent format anyway.
+    */
+   if (brw->gen >= 9 && srgb_enabled && mt->num_samples <= 1 &&
+       _mesa_get_srgb_format_linear(mt->format) != mt->format) {
+
+      /* Lossless compression is not supported for SRGB formats, it
+       * should be impossible to get here with such surfaces.
+       */
+      assert(!intel_miptree_is_lossless_compressed(brw, mt));
+      intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+                                   false, false);
+   }
+
+   /* For layered rendering non-compressed fast cleared buffers need to be
+    * resolved. Surface state can carry only one fast color clear value
+    * while each layer may have its own fast clear color value. For
+    * compressed buffers color value is available in the color buffer.
+    */
+   if (layer_count > 1 &&
+       !(mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
+       !intel_miptree_is_lossless_compressed(brw, mt)) {
+      assert(brw->gen >= 8);
+
+      intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+                                   false, false);
+   }
+}
+
+void
+intel_miptree_finish_render(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt, uint32_t level,
+                            uint32_t start_layer, uint32_t layer_count)
+{
+   assert(_mesa_is_format_color_format(mt->format));
+   intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
+                              mt->mcs_buf);
+}
+
 /**
  * Make it possible to share the BO backing the given miptree with another
  * process or another miptree.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 52008d73b73..5f3431c5bdd 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -1050,6 +1050,15 @@ intel_miptree_prepare_texture(struct brw_context *brw,
                               struct intel_mipmap_tree *mt,
                               mesa_format view_format,
                               bool *aux_supported_out);
+void
+intel_miptree_prepare_render(struct brw_context *brw,
+                             struct intel_mipmap_tree *mt, uint32_t level,
+                             uint32_t start_layer, uint32_t layer_count,
+                             bool srgb_enabled);
+void
+intel_miptree_finish_render(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt, uint32_t level,
+                            uint32_t start_layer, uint32_t layer_count);
 
 void
 intel_miptree_make_shareable(struct brw_context *brw,