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i965/vec4/tes: fix setup_payload() for 64bit data types
Use a width of 2 with 64-bit attributes.
Also, if we have a dvec3/4 attribute that gets split across two registers
such that components XY are stored in the second half of a register and
components ZW are stored in the first half of the next, we need to fix
regioning for any instruction that reads components Z/W of the attribute.
Notice this also means that we can't support sources that read cross-dvec2
swizzles (like XZ for example).
v2: don't assert that we have a single channel swizzle in the case that we
have to fix up Z/W access on the first half of the next register. We
can handle any swizzle that does not cross dvec2 boundaries, which
the double scalarization pass should have prevented anyway.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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1 changed files with 20 additions and 1 deletions
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@ -82,14 +82,33 @@ vec4_tes_visitor::setup_payload()
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if (inst->src[i].file != ATTR)
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continue;
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bool is_64bit = type_sz(inst->src[i].type) == 8;
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struct brw_reg grf =
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brw_vec4_grf(reg + inst->src[i].nr / 2, 4 * (inst->src[i].nr % 2));
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grf = stride(grf, 0, 4, 1);
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grf = stride(grf, 0, is_64bit ? 2 : 4, 1);
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grf.swizzle = inst->src[i].swizzle;
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grf.type = inst->src[i].type;
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grf.abs = inst->src[i].abs;
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grf.negate = inst->src[i].negate;
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/* For 64-bit attributes we can end up with components XY in the
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* second half of a register and components ZW in the first half
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* of the next. Fix it up here.
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*/
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if (is_64bit && grf.subnr > 0) {
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/* We can't do swizzles that mix XY and ZW channels in this case.
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* Such cases should have been handled by the scalarization pass.
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*/
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assert((brw_mask_for_swizzle(grf.swizzle) & 0x3) ^
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(brw_mask_for_swizzle(grf.swizzle) & 0xc));
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if (brw_mask_for_swizzle(grf.swizzle) & 0xc) {
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grf.subnr = 0;
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grf.nr++;
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grf.swizzle -= BRW_SWIZZLE_ZZZZ;
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}
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}
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inst->src[i] = grf;
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}
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}
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