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radv: only clear VRS_HTILE_ENCODING on GFX10.3+

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On older chips like GFX9, bit 19 is RB_ALIGNED.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5859
Fixes: 9c746157ae ("radv: reset VRS if the current subpass doesn't have a VRS attachment")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14530>
This commit is contained in:
Samuel Pitoiset 2022-01-13 08:51:20 +01:00 • committed by Marge Bot
parent fd2fbc558b
commit 49c1b40290
1 changed files with 2 additions and 1 deletions
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3
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1930,7 +1930,8 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_
db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
}
if (!cmd_buffer->state.subpass->vrs_attachment) {
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
!cmd_buffer->state.subpass->vrs_attachment) {
db_htile_surface &= C_028ABC_VRS_HTILE_ENCODING;
}