diff --git a/src/nouveau/compiler/nak/calc_instr_deps.rs b/src/nouveau/compiler/nak/calc_instr_deps.rs
index 61b5160bc2a..77c2831f1ee 100644
--- a/src/nouveau/compiler/nak/calc_instr_deps.rs
+++ b/src/nouveau/compiler/nak/calc_instr_deps.rs
@@ -551,7 +551,7 @@ impl TexQueueSimulationState {
 
         // If the flush needs a barrier, the queue will not be full,
         // therefore the push will not need a barrier.
-        debug_assert!(!flush_level.is_some() || !push_level.is_some());
+        debug_assert!(flush_level.is_none() || push_level.is_none());
         flush_level.or(push_level)
     }
 }
diff --git a/src/nouveau/compiler/nak/from_nir.rs b/src/nouveau/compiler/nak/from_nir.rs
index d02cdfdd167..a95a57d9398 100644
--- a/src/nouveau/compiler/nak/from_nir.rs
+++ b/src/nouveau/compiler/nak/from_nir.rs
@@ -2889,14 +2889,14 @@ impl<'a> ShaderFromNir<'a> {
                 };
 
                 for i in 0..32 {
-                    if !self.fs_out_regs[i].is_none() {
+                    if self.fs_out_regs[i].is_some() {
                         info.writes_color |= 1 << i;
                     }
                 }
                 let mask_idx = (NAK_FS_OUT_SAMPLE_MASK / 4) as usize;
-                info.writes_sample_mask = !self.fs_out_regs[mask_idx].is_none();
+                info.writes_sample_mask = self.fs_out_regs[mask_idx].is_some();
                 let depth_idx = (NAK_FS_OUT_DEPTH / 4) as usize;
-                info.writes_depth = !self.fs_out_regs[depth_idx].is_none();
+                info.writes_depth = self.fs_out_regs[depth_idx].is_some();
 
                 let mut srcs = Vec::new();
                 for i in 0..8 {