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intel: use generated workaround helpers for Wa_1409600907

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Wa_1409600907 was enabled for gen12+.  It should not be applied for
platforms after gen12.0.  Use generated helpers to ensure application
to all relevant platforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21743>
This commit is contained in:
Mark Janes 2023-02-07 14:16:33 -08:00 • committed by Marge Bot
parent 5691b10b0f
commit 4978db6b9e
4 changed files with 4 additions and 7 deletions
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2
src/gallium/drivers/iris/iris_state.c
View file

@ -8424,7 +8424,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
}
if (GFX_VER >= 12 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) {
if (INTEL_NEEDS_WA_1409600907 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) {
/* Wa_1409600907:
*
* "PIPE_CONTROL with Depth Stall Enable bit must be set

2
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1668,10 +1668,10 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
pipe.RenderTargetCacheFlushEnable =
bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
#if INTEL_NEEDS_WA_1409600907
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
#if GFX_VER >= 12
pipe.DepthStallEnable =
pipe.DepthCacheFlushEnable || (bits & ANV_PIPE_DEPTH_STALL_BIT);
#else

2
src/intel/vulkan/gfx8_cmd_buffer.c
View file

@ -55,7 +55,9 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
pc.RenderTargetCacheFlushEnable = true;
#if GFX_VER >= 12
pc.TileCacheFlushEnable = true;
#endif
#if INTEL_NEEDS_WA_1409600907
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/

5
src/intel/vulkan_hasvk/genX_cmd_buffer.c
View file

@ -1727,11 +1727,6 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
pipe.RenderTargetCacheFlushEnable =
bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
#if GFX_VER == 8
/* From Broadwell PRM, volume 2a: